GPU Physical Design Clocking Engineer

What you'll do

• Implement complete chip design from netlist to tapeout for high-performance GPUs and SoCs.
• Design and implement high-speed clock distribution networks from the root to the leaf.
• Optimize clocking construction to improve performance, power, and area (PPA) metrics.
• Develop and enforce clocking methodologies, guidelines, and checklists to streamline physical design workflows.
• Resolve complex cross-hierarchy clocking issues involving latency, skew, and variation.
• Integrate internal and external IP while specifying requirements in the physical domain.
• Design and craft test structures to evaluate clocking functionality and performance post-silicon.
• Manage multi-voltage and multi-clock domain integration including ESD solutions and mixed-signal blocks.

What we're looking for

• Bachelor of Science degree and 10 years of relevant experience.
• Experience with ASIC integration including floorplanning, clock and power distribution, global signal planning, and I/O planning.
• Experience with floorplanning tools, P&R flows, and global timing verification flows.
• Experience with hierarchical design approach, top-down design, budgeting, timing, and physical convergence (preferred).
• Experience planning, implementing, and analyzing high-speed clock distribution networks from root to leaf (preferred).
• Exposure to various clock distribution strategies including balanced trees, mesh, and forwarded clocks (preferred).
• Ability to use critical clock metrics like latency, skew, and variation to solve cross-hierarchy issues (preferred).
• Experience with large subsystem designs (>20M gates) at frequencies over 1GHz using new technologies (preferred).