GPU Physical Design Engineer, STA/Timing

Apple Inc

Confirmed live yesterday High trust

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Work type
On-site
Location
Austin, TX
Posted
11 days ago
Freshness
Confirmed live yesterday

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Similar $206k
$147k most similar roles pay here $258k

This listing doesn't post a salary. Most similar roles pay $177,250–$233,987.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2240 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1831 roles with salary data.

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TL;DR · GPU Physical Design Engineer, STA/Timing

As a GPU Physical Design Engineer, STA/Timing within the Silicon Engineering group, you will be responsible for the timing closure of highly complex GPU designs. You will serve as a central point of contact for RTL and architecture teams to define physical design constraints while partnering with Synthesis and Physical Design teams to optimize for power, performance, and timing. Your daily responsibilities include setting up DFT modes, assembling top-level designs for STA, creating automation scripts, running ECO flows, and performing signoff checks for tapeout activities. You will work with CAD and vendors to improve analysis flows. Required skills include experience in physical design, synthesis, DFT, or clocking, along with proficiency in scripting languages like TCL, Python, Perl, or shell. Technical expertise includes digital logic design, RTL, CMOS transistor logics, VLSI concepts, and advanced features like XALK and POCVM.

What you'll do

  • Coordinate with RTL and architecture teams to define physical design constraints for backend flows.
  • Partner with synthesis and physical design teams to optimize designs for power, performance, and timing.
  • Configure DFT modes and ensure all test features are properly timed.
  • Assemble top-level designs for STA by reviewing logs and reports to ensure accurate analysis.
  • Develop and maintain scripts and automation tools to improve the quality of STA reports.
  • Execute ECO flows to achieve final timing closure on complex GPU designs.
  • Perform a full suite of signoff checks to support tapeout activities and ensure manufacturing quality.
  • Collaborate with CAD teams and vendors to enhance analysis flows and integrate new features.

What we're looking for

  • Bachelor's degree in Computer Science or Computer Engineering required.
  • Master's degree preferred.
  • Experience or coursework in physical design, synthesis, DFT, or clocking.
  • Experience or coursework with digital logic design, RTL, DV, CMOS transistor logics, or VLSI concepts.
  • Experience with scripting languages such as TCL, Python, Perl, or shell scripting.
  • Internship or prior work experience in timing closure or physical design (preferred).
  • Experience working with EDA tools and exposure to their APIs (preferred).
  • Exposure to advanced concepts like XALK, POCVM, ETMs, or large volume data analysis (preferred).

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