Physical Design/Implementation Engineer, Staff

Qualcomm

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Quick summary

Work type
On-site
Location
Austin, TX
Salary
$145,600–$218,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $182k
$132k $275k
below market most similar roles pay here above market

This role pays less than 65% of similar roles. Most pay $175,057–$233,050 — the blue band above. At the midpoint, this role pays about $182k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Physical Design/Implementation Engineer, Staff

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The Physical Design/Implementation Engineer-Staff joins the ASICS Engineering group to drive end-to-end PPA optimization across the synthesis-to-PnR boundary. This role involves managing floorplanning, placement, clock tree synthesis, and routing while addressing advanced node challenges like multi-patterning and pin access. The engineer will perform aggressive area recovery, leakage reduction, and performance pushes for multi-clock domain and multi-corner multi-mode designs. Key responsibilities include writing timing constraints, implementing low-power designs using UPF, and managing power optimization flows like clock gating and Vt swapping. Required technical skills include proficiency in Python, Tcl, and AI usage, alongside experience with Fusion Compiler, Genus, Innovus, and ICC2. The position requires deep knowledge of Static Timing Analysis, Equivalence Checking, and high-speed, low-power processor design to solve complex physical implementation problems.

Skills

ASIC Design Physical Design Synthesis PnR Static Timing Analysis STA Clock Tree Synthesis CTS Floorplanning Routing UPF low-power design Python Tcl Fusion Compiler Genus Innovus ICC2 PrimeTime Tempus LEC Version Control Configuration Management Regression

What you'll do

  • Drive end-to-end PPA optimization across the synthesis-to-PnR boundary using industry-standard tools.
  • Execute floorplanning, placement, clock tree synthesis, and routing on advanced technology nodes.
  • Write and tune timing constraints for synthesis, STA, and physical closure to optimize performance.
  • Perform aggressive area recovery and leakage/dynamic power reduction to meet PPA targets.
  • Manage timing closure for multi-clock domain and multi-corner multi-mode (MCMM) designs.
  • Implement low-power design features including power gating, multi-voltage domains, and level shifters using UPF.
  • Apply power optimization techniques such as clock gating, cell sizing, and Vt swapping.
  • Utilize Python and Tcl scripts to automate design flows and manage configuration.

What we're looking for

  • 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.
  • Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC experience, or Master's with 3+ years, or PhD with 2+ years.
  • In-depth knowledge of Physical Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing using industry-standard tools.
  • Experience with advanced technology nodes, including multi-patterning, pin access, cell legalization, and advanced DRC rules.
  • Experience with timing constraints for synthesis, STA, timing closure, and pipelining for performance optimization.
  • Proficiency in low-power design implementation using UPF, including power gating and multi-voltage domains.
  • Proficiency in Python/Tcl and AI usage, with familiarity with Version Control, Configuration Management, and Regression.
  • Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science (preferred).

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