This role pays less than
70%
of similar roles. Most pay
$172,500–$222,000
— the shaded band above.
At the midpoint, this role pays about
$175k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
As a Physical Design/Implementation Engineer-Staff within the ASICS Engineering group, you will drive end-to-end PPA optimization across the synthesis-to-PnR boundary rather than treating it as a simple handoff. You will be responsible for floorplanning, placement, clock tree synthesis, routing, and timing closure for multi-clock domain, multi-corner, and multi-mode designs. Your daily work involves managing advanced node challenges like multi-patterning and DRC rules while performing aggressive area recovery and power reduction. You will utilize industry-standard tools including Innovus, ICC2, Fusion Compiler, Genus, PrimeTime, and Tempus. The role requires proficiency in Python, Tcl, and AI usage to navigate complex VLSI front-end and back-end steps. You will solve critical hardware problems involving low-power design implementation using UPF, power gating, and multi-voltage domains for high-speed, low-power processor designs.
Drive end-to-end PPA optimization across the synthesis-to-PnR boundary for advanced technology nodes.
Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools.
Write and tune timing constraints for synthesis, STA, and pipelining to ensure performance goals are met.
Perform aggressive area recovery and reduce leakage/dynamic power through cell sizing and Vt swapping.
Implement low-power designs using UPF, including power gating and multi-voltage domain management.
Resolve complex timing issues for multi-clock domain and multi-corner multi-mode (MCMM) designs.
Manage physical design constraints such as multi-patterning, pin access, and advanced DRC rules.
What we're looking for
Bachelor's degree in Science or Engineering with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years of ASIC related experience.
5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.
In-depth knowledge of Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and moving across the synthesis-to-PnR boundary for PPA optimization.
Experience with advanced technology nodes including multi-patterning, pin access, cell legalization, and advanced DRC rules.
Proficiency in writing and tuning timing constraints for synthesis, STA, timing closure, and pipelining.
Knowledge of low-power design implementation using UPF, power gating, multi-voltage domains, and various power optimization techniques.
Proficiency in Python/Tcl and familiarity with standard software engineering practices like Version Control and Configuration Management.
Familiarity with PnR tools (Innovus/ICC2), Synthesis tools (Fusion Compiler/Genus), and STA tools (PrimeTime/Tempus).