Physical Design Engineer, DSP Team

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $164,000–$246,000 / yr
Posted: 156 days ago
Freshness: Confirmed live yesterday
Closes: Oct 5, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k

This role $205k

$132k most similar roles pay here $258k

This role pays more than 58% of similar roles. Most pay $162,000–$216,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer, DSP Team

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Physical Design Engineer - DSP Team The Physical Design Engineer - DSP Team member will focus on activities related to synthesis, structured placement, and clock tree synthesis while managing physical design convergence deliverables. This role involves updating implementation flows for optimal power, performance, and area, as well as developing semi-custom design techniques to maximize utilization and efficiency. The engineer will use scripting to extend methodologies and perform advanced power checks on multiple complex blocks to ensure specifications are met. Key technical requirements include proficiency in P&R, timing analysis, and CAD tools such as Synopsys Fusion Compiler, Design Compiler, ICC2, Cadence Genus, or Innovus. The role addresses the challenge of driving high-speed design implementation through logic optimization, clock structures, and power optimization to achieve superior performance for complex integrated circuit designs within a specialized DSP domain.

Skills

ASIC Physical Design Synthesis P&R Timing Analysis Fusion Compiler Synopsys FC ICC2 Cadence Genus Innovus Scripting Logic Optimization Clock Tree Synthesis Power Optimization Physical Design Convergence

What you'll do

Update physical implementation flows to optimize power, performance, and area (PPA).
Develop semi-custom design techniques to maximize utilization and power efficiency.
Create and enhance design methodologies using scripting to achieve optimal PPA.
Execute advanced architecture and design of complex blocks using tools like Fusion Compiler.
Perform advanced power checks on multiple blocks to ensure designs meet specifications.
Resolve complex technical issues using deductive and inductive problem-solving techniques.
Innovate new processes and procedures to achieve established physical design objectives.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
12+ years of experience in ASIC Physical design, Synthesis, or related work.
Strong proficiency in P&R, timing analysis, and CAD tools like Synopsys FC/DC, ICC2, Cadence Genus, or Innovus.
Very good understanding of Logic optimization for high-speed design, clock structures, and power optimization.
Advanced experience with scripting tools and programming languages.
Experience in CPU or GPU design or related work.
Ability to use advanced data analysis and interpretation skills to solve complex problems.
Strong verbal and written communication skills to convey technical information to diverse audiences.

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