Physical Design Engineer, DSP Team

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $174,400–$261,600 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k

This role $218k

$137k $275k

below market most similar roles pay here above market

This role pays more than 67% of similar roles. Most pay $172,000–$234,737 — the blue band above. At the midpoint, this role pays about $218k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Physical Design Engineer, DSP Team

Role Posting Log in to save

The Physical Design Engineer - DSP Team joins the ASICS Engineering group to execute critical physical implementation tasks. This role focuses on synthesis, structured placement, and clock tree synthesis to achieve physical design convergence. The engineer will update implementation flows for optimum power, performance, and area while developing semi-custom design techniques to maximize utilization. Daily responsibilities include using scripting to enhance design methodologies, running advanced power checks on complex blocks, and collaborating with logic teams to solve high-speed design problems. Required technical skills include proficiency in P&R, timing analysis, and CAD tools such as Synopsys FC/DC, ICC2, or Cadence Genus and Innovus. The work involves logic optimization to drive high-speed implementation, clock structures, and power optimization for complex blocks within the DSP domain.

What does a Physical Design Engineer earn?

Median $177300 from 31 postings across 9 companies.

See salary data

Skills

ASIC Physical Design Synthesis Clock Tree Synthesis CTS P&R Timing Analysis Fusion Compiler Cadence Genus Logic Optimization Scripting Power Optimization PPA CAD Tools

What you'll do

Update physical implementation flows to optimize power, performance, and area.
Develop semi-custom design techniques to maximize utilization and power efficiency.
Enhance design methodologies and PPA through custom scripting.
Execute advanced architecture and design for multiple complex blocks using tools like Fusion Compiler.
Run advanced power checks on multiple blocks to ensure design specifications are met.
Innovate new processes and procedures to achieve established design objectives.
Use deductive and inductive problem-solving to resolve issues with missing or conflicting information.

What we're looking for

Bachelor's degree in Science, Engineering, or related field.
12+ years of ASIC Physical design, Synthesis, or related work experience.
Strong proficiency in P&R, timing analysis, and CAD tools like Synopsys FC/DC, ICC2, or Cadence Genus and Innovus.
Very good understanding of Logic optimization for high-speed design, clock structures, and power optimization.
Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering (preferred).
15+ years of CPU or GPU design or related work experience (preferred).
10+ years of experience with architecture and design tools (preferred).
10+ years of experience with scripting tools and programming languages (preferred).

Similar roles

Physical Design/Implementation Engineer, Staff

Qualcomm

Austin, TX 40 days ago $145,600–$218,400

ASIC Design Physical Design Synthesis PnR Static Timing Analysis STA Clock Tree Synthesis CTS Floorplanning Routing UPF low-power design Python Tcl Fusion Compiler Genus Innovus ICC2 PrimeTime Tempus LEC Version Control Configuration Management Regression

4+ yrs exp

Save

Physical Design Engineer

Qualcomm

San Diego, CA 8 days ago $174,400–$261,600

ASIC SoC Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python Perl TCL C/C++ Shell Scripting Linux Unix Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis

10+ yrs exp

Save

Physical Design

Qualcomm

San Diego, CA 25 days ago $121,800–$182,600

ASIC Design Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis Linux Unix

2+ yrs exp

Save

Physical Design Engineer

Qualcomm

San Diego, CA +2 40 days ago $123,100–$250,000

ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation

4+ yrs exp

Save

Physical Design Engineer

Broadcom

San Jose, CA 64 days ago

Physical Layout 3D IC TCL Python DRC LVS RDL MCM PCB Layout Electrical Analysis Advanced Packaging

10+ yrs exp

Save

Physical Design Engineer

Broadcom

San Jose, CA 64 days ago

Physical Layout 3D IC TCL Python DRC LVS Electrical Analysis SI PI RDL MCM PCB Layout Advanced Packaging

10+ yrs exp

Save