Staff SOC Physical Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$152,360–$210,000 / yr
Posted
15 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k
This role $181k
$139k most similar roles pay here $277k

This role pays less than 68% of similar roles. Most pay $177,250–$234,725 — the shaded band above. At the midpoint, this role pays about $181k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $152,130–$222,500 across 550 roles with salary data.

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At a glance

TL;DR · Staff SOC Physical Design Engineer

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The Staff SOC Physical Design Engineer joins the ASICS Engineering team to manage complex physical design flows for system-on-chip products. This individual handles high-speed DDR, graphics, micro-architecture, and SoC algorithm design while focusing on target power utilization and performance optimization. Daily responsibilities include floor planning, clock tree synthesis, place and route, PDN, and timing analysis. The role involves performing critical physical verification checks such as LVS, DRC, design-for-manufacturing, and design-for-yield at both the chip and block levels. This position requires coordinating cross-functional engineering efforts to achieve signoff closure for tapeout while participating in design reviews and project meetings. The work centers on solving technical challenges related to power optimization and physical verification within high-performance SoC architectures, requiring expertise in advanced physical design methodologies and complex hardware integration requirements.

Skills

Physical Design DDR Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC SoC Micro-architecture

What you'll do

  • Manage physical design flows for high-speed DDR, graphics, and micro-architecture.
  • Execute floor planning, clock tree synthesis, place and route, and power delivery network (PDN) tasks.
  • Perform timing analysis and closure to optimize power and performance for SoC products.
  • Conduct physical verification checks including LVS, DRC, DFM, and D1Y at chip and block levels.
  • Develop and implement design models and methodologies for SOC algorithm designs.
  • Provide schedules and lead cross-functional engineering efforts to achieve signoff for tapeout.
  • Communicate development plans and contribute technical expertise during design reviews and project meetings.

What we're looking for

  • A Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is accepted.
  • Candidates must have three years of experience in a related occupation.
  • Experience in Physical Design Flow for high-speed DDR and graphics is required.
  • Proficiency in floor planning, clock tree synthesis, place and route, and PDN is required.
  • Expertise in timing analysis, closure, and physical verification checks (LVS, DRC, DFM, and D1Y) is required.
  • Experience in micro-architecture, SoC algorithm design, modeling, and methodology is required.
  • Ability to manage project schedules and provide cross-functional support for tapeout signoff is required.

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