Physical Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CAAustin, TXSanta Clara, CA
Salary: $123,100–$250,000 / yr
Posted: 40 days ago
Freshness: Confirmed live yesterday
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $187k

$108k $265k

below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $168,200–$230,700 — the blue band above. At the midpoint, this role pays about $187k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Physical Design Engineer

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JOB TITLE: Physical Design Engineer (Engineer up to Principal Level) The Physical Design team within the Digital ASIC organization seeks engineers to develop and execute advanced physical design methodologies for high-performance, low-power SoCs and IP blocks. Candidates will handle floorplanning, power planning, place and route, clock tree synthesis, timing closure, signal integrity analysis, and physical verification. The role involves implementing designs from synthesis through final tapeout while collaborating with architecture, RTL, DFT, verification, CAD, and product engineering teams. Key technical requirements include proficiency in Linux/Unix environments and scripting using Python, Tcl, Perl, or Shell. Candidates should possess expertise in Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime. This position addresses complex power, performance, area, and scalability challenges across GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, and Audio technologies.

What does a Physical Design Engineer earn?

Median $177300 from 31 postings across 9 companies.

See salary data

Skills

ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation

What you'll do

Execute floorplanning, power planning, placement, clock tree synthesis, and routing for ASIC and SoC blocks.
Drive timing closure, power optimization, and signal integrity analysis across multiple operating modes and corners.
Perform physical verification and implement ECOs to ensure design signoff.
Develop scripts and automation solutions using Python, Tcl, or Perl to improve design productivity.
Analyze and resolve complex physical design issues impacting schedule, quality, or performance targets.
Define and implement scalable physical design methodologies and flows for advanced process nodes.
Lead the implementation and signoff of complex subsystems and full-chip partitions.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design experience.
Experience with digital ASIC physical implementation methodologies and understanding of power, performance, area, and timing tradeoffs.
Experience working in Linux/Unix environments.
Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.
Experience with complete Physical Design Flow from synthesis through tapeout (preferred).
Experience using Cadence Innovus, Synopsys Fusion Compiler, or Synopsys PrimeTime (preferred).

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