Physical Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TXSanta Clara, CA
Salary
$123,100–$250,000 / yr
Posted
25 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 13, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $187k
$108k most similar roles pay here $265k

This role pays more than 52% of similar roles. Most pay $163,000–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

Physical Design Engineer (Engineer up to Principal Level) joins the Digital ASIC organization to develop advanced physical design methodologies for high-performance, low-power SoCs and IP blocks. The role involves executing floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure while addressing signal integrity and physical verification. Candidates will collaborate with cross-functional teams including RTL, DFT, and CAD to deliver designs from synthesis through final tapeout. Key technical requirements include proficiency in Linux/Unix environments and scripting using Python, Tcl, Perl, or Shell. Preferred skills include experience with Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime for static timing analysis. The work focuses on solving complex power, performance, area, and scalability challenges across diverse product areas including GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, and Audio technologies using advanced process nodes.

What you'll do

  • Execute floorplanning, power planning, placement, clock tree synthesis, and routing for complex SoC blocks.
  • Perform timing analysis, signal integrity analysis, and physical verification to ensure design closure.
  • Resolve technical challenges related to congestion, power optimization, and multi-mode operating constraints.
  • Develop scripts and automation solutions using Python, Tcl, or Perl to improve design productivity.
  • Implement low-power design techniques and manage power domain analysis for advanced nodes.
  • Drive the physical implementation process from initial synthesis through final tapeout.
  • Create and maintain scalable methodologies and flow improvements across multiple engineering teams.

What we're looking for

  • Bachelor's degree in Engineering or a related field with 4+ years of experience, OR Master's with 3+ years, OR PhD with 2+ years.
  • Experience in digital ASIC physical implementation methodologies.
  • Understanding of power, performance, area, timing, and physical design tradeoffs.
  • Proficiency working in Linux/Unix environments.
  • Programming or scripting experience using Python, Tcl, Perl, Shell, or similar languages.
  • Strong analytical, problem-solving, and debugging skills.
  • Experience with complete Physical Design Flow from synthesis through tapeout (preferred).
  • Expertise in floorplanning, power planning, placement, CTS, routing, timing optimization, and closure (preferred).

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