ASIC Physical Design Engineer

Cisco

Confirmed live today High trust

Closes in 7 days

Quick summary

Work type: On-site
Location: San Jose, CAAustin, TXRTP, North Carolina
Employment: Full-time
Posted: 11 days ago
Freshness: Confirmed live today
Closes: Oct 9, 2026 (soon)
Nearby: 99+ roles within 25 mi

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Similar $199k

$137k most similar roles pay here $273k

This listing doesn't post a salary. Most similar roles pay $168,425–$229,650.

Based on 240 similar postings.

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About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 205 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 158 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer

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As an ASIC Physical Design Engineer within the Common Hardware Group, you will drive the RTL-to-GDSII implementation flow for advanced semiconductor nodes ranging from sub-16nm to 2nm. You will be responsible for executing hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies for high-performance networking chips. Your daily work involves performing static timing analysis, managing timing ECO strategies, and identifying improvements in backend design flows. To succeed, you must possess expertise in physical design, including power integrity analysis and large-scale designs exceeding 100M gates. The role requires proficiency with tools such as PrimeTime, Innovus, Genus, Formality, Redhawk, and Calibre. Additionally, you will utilize scripting languages like TCL and Python to automate processes while collaborating with RTL, DFT, and EDA teams to ensure successful chip delivery.

Skills

ASIC RTL-to-GDSII Floorplanning Place and Route Static Timing Analysis PrimeTime TCL Python Cadence Innovus Cadence Genus Synopsys Formality Mentor Calibre Apache Redhawk Voltus Physical Verification

What you'll do

Own and drive the full RTL-to-GDSII implementation flow for advanced semiconductor nodes.
Execute hierarchical floor planning, place and route, and clock and power distribution strategies.
Perform static timing analysis (STA) and manage timing ECO strategies using industry-standard tools.
Develop automated scripts within STA tools to improve design efficiency.
Analyze quality and efficiency gaps to recommend improvements for tools, flows, and methodologies.
Collaborate with RTL, DFT, and EDA vendors to drive implementation efficiency.
Evaluate and implement new timing methodologies while providing creative debugging solutions.

What we're looking for

Bachelor's degree in Electrical Engineering plus 5 years of experience, Master's plus 2 years, or PhD with no experience required.
Hands-on experience in ASIC physical design and implementation is required.
Experience with hierarchical floorplanning, clock/power distribution, signal/IO planning, and timing closure is required.
Prior experience with power integrity analysis and designs exceeding 100M gates in advanced nodes (sub-16nm) is required.
Scripting skills using languages such as TCL or Python are preferred.
Experience with Place & Route tools like Cadence Innovus or Synopsys FC is preferred.
Synthesis experience including Cadence Genus or Synopsys FC is preferred.
Experience with Static Timing Analysis, Formal Verification, and Physical Verification tools is preferred.