CPU Server Physical Design Clock Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$148,300–$222,500 / yr
Posted
87 days ago
Freshness
Confirmed live yesterday
Closes
Dec 13, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $185k
$139k most similar roles pay here $240k

This role pays less than 51% of similar roles. Most pay $168,500–$223,700 — the shaded band above. At the midpoint, this role pays about $185k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Clock Engineer

As a CPU Server Physical Design Clock Engineer within the CPU Engineering group, you will collaborate with microarchitecture, RTL design, CAD, and block-level physical design teams to develop best-in-class clocking solutions for next-generation CPUs. Your daily responsibilities include driving overall clock generation and distribution methodologies, implementing techniques to optimize skew and power, and performing jitter analysis and measurements to provide critical feedback to engineers. You will work on the construction of low skew and low power clock systems using H-tree, mesh, spines, and CTS implementations. The role requires expertise in device physics, RC delay, electrical aspects, and SPICE simulation for circuit design and verification. Key technical competencies include standard cell optimizations, PLL specifications, and experience with deep submicron process technology nodes to solve complex timing and power challenges in high-performance processor designs.

What you'll do

  • Design, implement, and validate CPU clocking solutions for next-generation processors.
  • Drive the overall methodology for clock generation and distribution across CPU designs.
  • Implement clocking techniques to optimize skew and power in collaboration with CAD and block designers.
  • Perform jitter analysis and measurements to identify necessary fixes for physical design engineers.
  • Construct and analyze low-skew, low-power clock networks including H-trees, meshes, and spines.
  • Conduct SPICE simulations and analyses for circuit design and verification.
  • Define and maintain clock methodologies across various product designs.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ years of experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of experience.
  • Experience in construction and analysis of low skew and low power clock generation and distribution.
  • Experience in clock H-tree, mesh, spines, and CTS implementations.
  • Proficiency in SPICE simulation and analysis for circuit design and verification.
  • Understanding of device physics, RC delay, and electrical aspects.
  • Expertise in chip physical design, standard cell optimizations, and deep submicron process technology nodes.

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