CPU Server Physical Design Clock Engineer

Qualcomm

Quick summary

Work type: On-site
Location: Austin, TXSanta Clara, CA
Salary: $148,300–$222,500 / yr
Posted: 2 days ago
Closes: Dec 13, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $185k

$137k most similar roles pay here $253k

This role pays less than 57% of similar roles. Most pay $168,500–$225,600 — the shaded band above. At the midpoint, this role pays about $185k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 757 open roles on FindRole.

Listed pay typically runs $151,900–$229,800 across 444 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Clock Engineer

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As a Physical Design Clock Engineer at Qualcomm Technologies, you will collaborate with microarchitecture, RTL design, CAD, and physical design teams to develop cutting-edge clocking solutions for next-generation CPUs. Your responsibilities include constructing and analyzing low skew and low power clocks, implementing H-tree, mesh, spines, and CTS designs, and conducting SPICE simulations. You will define clock methodologies across various projects, optimize standard cells, and work with deep submicron process technologies. Proficiency in PLL specifications, jitter analysis, and communication skills are essential for driving clock generation and distribution strategies, collaborating on design optimizations, and providing critical feedback to enhance overall chip performance.

Skills

SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clock_Tree_Synthesis HDL Verilog SystemVerilog Cadence Synopsys Calibre

What you'll do

Analyze and implement low skew and low power clock generation for CPUs.
Design and optimize H-tree, mesh, spines, and CTS implementations in physical design.
Conduct SPICE simulations to verify circuit designs and ensure electrical integrity.
Collaborate with CAD teams to optimize clocking techniques for reduced skew and power.
Perform jitter analysis and provide feedback on necessary fixes for block level designs.

What we're looking for

Experience in low skew and low power clock generation and distribution.
Proficiency in clock H-tree, mesh, spines, and CTS implementations.
Strong understanding of device physics, RC delay, and electrical aspects.
Skilled in SPICE simulation for circuit design and verification.
MS in Electrical Engineering with 8+ years of practical experience.
Defined clock methodology across various designs and technologies.
Proficient in PLL specifications, clock skew estimation, and jitter measurements.

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