CPU Physical Design Timing Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 88% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $196k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
As a CPU Physical Design Timing Engineer within the CPU Engineering group, you will define, develop, and drive timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to establish timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domains, as well as conducting timing analysis and debug across various PVT conditions. You will develop automation scripts using TCL, Perl, and Python to enhance CPU timing infrastructure and methodology. The role requires proficiency with industry tools such as PrimeTime, Tempus, ICC2, and Innovus. You will address technical challenges involving Spice to STA correlation, crosstalk noise, signal integrity, and layout parasitic extraction while working on advanced N2/N3 technology nodes.
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