CPU Physical Design Timing Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$122,500–$183,700 / yr
Posted
4 days ago
Closes
Dec 26, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $153k
$110k most similar roles pay here $238k

This role pays less than 79% of similar roles. Most pay $161,900–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 542 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 521 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Timing Engineer

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As a CPU Physical Design Timing Engineer at Qualcomm Technologies, Inc., you will join the Oryon CPU Cores team to drive timing closure for cutting-edge CPUs on advanced technology nodes like N2 and N3. Your daily tasks include developing timing constraints, scripting with TCL/Perl/Python, and optimizing STA flows using tools such as PrimeTime and Tempus. You will collaborate closely with microarchitecture and RTL design teams to ensure power, area, and performance goals are met across multiple voltage domains. Additionally, you will evaluate methodologies and propose solutions for timing issues, contributing to the overall PPA (Power, Performance, Area) objectives of Qualcomm’s CPU projects. Essential skills include strong automation capabilities, STA tool proficiency, and experience with digital flow design implementation from RTL to GDS.

Skills

TCL Perl Python PT Tempus Prime-time ICC2 Innovus CI/CD STA AOCV POCV CTS Latch transparency handling Multi-cycle path handling Crosstalk noise Signal Integrity Layout Parasitic Extraction Feed through handling

What you'll do

  • Define and develop timing constraints for Oryon CPU cores.
  • Drive implementation to meet power, area, and performance goals using industry tools.
  • Code scripts with STA native tools to enable CPU timing infrastructure.
  • Conduct timing analysis and validation across multiple PVT conditions.
  • Optimize STA flow and correlate Spice models with timing analysis results.
  • Identify root causes of timing discrepancies and propose solutions.
  • Evaluate various timing methodologies on different designs and technology nodes.

What we're looking for

  • Extensive experience with TCL/Perl/Python for automation in CPU physical design.
  • Proficient in developing and optimizing STA signoff flow using industry-standard tools.
  • Strong background in timing analysis, validation, and debug across multiple PVT conditions.
  • Expertise in PrimeTime and Tempus for STA flow optimization and Spice to STA correlation.
  • Deep understanding of digital flow implementation from RTL to GDS with ICC2 and Innovus.
  • Hands-on experience driving timing convergence at chip-level and hard-macro level designs.
  • Knowledge of crosstalk noise, signal integrity, layout parasitic extraction, and feed-through handling.

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