CPU Physical Design Timing Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$122,500–$183,700 / yr
Posted
74 days ago
Freshness
Confirmed live yesterday
Closes
Dec 26, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $153k
$110k most similar roles pay here $243k

This role pays less than 88% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Timing Engineer

As a CPU Physical Design Timing Engineer within the CPU Engineering group, you will define, develop, and drive timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to establish timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domains, as well as conducting timing analysis and debug across various PVT conditions. You will develop automation scripts using TCL, Perl, and Python to enhance CPU timing infrastructure and methodology. The role requires proficiency with industry tools such as PrimeTime, Tempus, ICC2, and Innovus. You will address technical challenges involving Spice to STA correlation, crosstalk noise, signal integrity, and layout parasitic extraction while working on advanced N2/N3 technology nodes.

What you'll do

  • Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
  • Conduct timing analysis, validation, and debug across multiple PVT conditions using PT or Tempus tools.
  • Execute Primetime or Tempus runs for STA flow optimization and Spice to STA correlation.
  • Identify root causes of timing miscorrelations at various design levels and propose technical solutions.
  • Evaluate different timing methodologies and tools across various designs and advanced technology nodes.
  • Develop automation scripts using TCL, Perl, or Python to support CPU STA signoff flows and infrastructure.
  • Define and manage timing constraints to meet aggressive power, area, and performance goals.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of relevant experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of relevant experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Excellent automation skills using TCL, Perl, and Python to develop STA signoff flow and methodology scripts.
  • Experience with STA tools such as PrimeTime and Tempus for timing analysis, validation, and debug.
  • Familiarity with digital flow design implementation from RTL to GDS using ICC2 or Innovus.
  • Expertise in STA basics including AOCV/POCV concepts, CTS, and managing timing constraints.
  • Knowledge of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, and device physics.

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