CPU Physical Design Timing Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 85% of similar roles. Most pay $169,337–$229,100 — the blue band above. At the midpoint, this role pays about $162k versus about $199k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 575 open roles on FindRole.
Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.
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At a glance
JOB TITLE: CPU Physical Design Timing Engineer (Austin, TX) As a CPU Physical Design Timing Engineer within the CPU Engineering group, you will define and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domains, as well as debugging timing miscorrelations across various PVT conditions. You will utilize industry-standard tools including PT, Tempus, ICC2, and Innovus. Key technical requirements involve coding automation scripts using TCL, Perl, and Python to develop CPU STA signoff flows. This role addresses critical timing methodology and PPA goals for advanced technology nodes N2 and N3.
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