CPU Physical Design Timing Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$129,500–$194,300 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $162k
$115k $264k
below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $169,337–$229,100 — the blue band above. At the midpoint, this role pays about $162k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU Physical Design Timing Engineer

JOB TITLE: CPU Physical Design Timing Engineer (Austin, TX) As a CPU Physical Design Timing Engineer within the CPU Engineering group, you will define and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and implement designs that meet aggressive power, area, and performance goals. Your daily responsibilities include performing STA setup, convergence, and signoff for multi-mode, multi-voltage domains, as well as debugging timing miscorrelations across various PVT conditions. You will utilize industry-standard tools including PT, Tempus, ICC2, and Innovus. Key technical requirements involve coding automation scripts using TCL, Perl, and Python to develop CPU STA signoff flows. This role addresses critical timing methodology and PPA goals for advanced technology nodes N2 and N3.

What you'll do

  • Define and develop timing constraints for Oryon CPU Cores to meet power, area, and performance goals.
  • Perform STA setup, convergence reviews, and signoff for multi-mode and multi-voltage domain designs.
  • Conduct timing analysis, validation, and debug across multiple PVT conditions using PT and Tempus tools.
  • Execute Primetime and Tempus flows for STA optimization and perform Spice to STA correlation.
  • Identify root causes of timing miscorrelation at various design levels and propose technical solutions.
  • Develop automation scripts using TCL, Perl, or Python to enable CPU timing infrastructure and signoff flows.
  • Evaluate various timing methodologies and tools across different designs and technology nodes.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of relevant work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Excellent automation skills using TCL, Perl, and Python.
  • Ability to develop automation scripts for CPU STA signoff flow and methodology.
  • Familiarity with digital flow design implementation from RTL to GDS using ICC, Innovus, and PT/Tempus.
  • Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, and managing timing constraints (preferred).
  • Hands-on experience with Prime-time and Tempus tools, and knowledge of ASIC back-end design flows (preferred).

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