Senior Staff CPU Physical Design CAD Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXSan Diego, CA
Salary
$198,700–$298,100 / yr
Posted
43 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 26, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $248k
$148k most similar roles pay here $314k

This role pays more than 88% of similar roles. Most pay $177,250–$227,300 — the shaded band above. At the midpoint, this role pays about $248k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Senior Staff CPU Physical Design CAD Engineer

As a Sr. Staff CPU Physical Design CAD Engineer within the CPU Engineering team, you will build and support high-performance implementation tools and flows to ensure custom CPUs achieve industry-leading power, performance, and area. Your daily responsibilities include developing, integrating, and releasing new features in place-and-route CAD flows, recommending methodology improvements, and debugging complex project-specific issues while collaborating with global teams and EDA vendors. You will utilize Tcl, Python, and automation to manage and regress flow designs for advanced technology nodes at 5nm or lower. The role requires expertise in digital design, timing analysis, physical verification, and industry-standard tools like Cadence Innovus. This position focuses on solving critical hardware challenges by optimizing the transition from conceptual architecture to productized silicon through sophisticated physical design methodologies and technical documentation.

What you'll do

  • Develop, integrate, and release new features in the high-performance place-and-route CAD flow.
  • Architect and recommend methodology improvements to optimize power, performance, and area for silicon designs.
  • Maintain, support, and debug implementation flows while resolving project-specific technical issues.
  • Provide methodology guidance and tool support to global CPU physical design teams.
  • Collaborate with EDA vendors to define roadmaps and resolve specific tool issues.
  • Write detailed technical documentation for complex CPU designs and review the work of junior engineers.
  • Solve highly complex problems to ensure design completeness, functionality, power, and performance.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 6+ years of relevant experience.
  • Master's degree in Electrical/Electronics Engineering or Computer Science with 5+ years of relevant experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ years of relevant experience.
  • Ten or more years of hands-on experience in place-and-route of high-performance chips in a design or CAD role.
  • High level of proficiency in Tcl and Python for automation tasks.
  • Experience with advanced technology nodes at 5nm or lower.
  • Solid understanding of digital design, timing analysis, physical verification, and industry-standard tools like Cadence Innovus.
  • Proven track record of managing and regressing place-and-route flows.

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