Sr. Staff CPU Physical Design CAD Engineer

Qualcomm

Actively hiring
Santa Clara, CA · Austin, TX Posted 26 days ago Apply by Nov 4, 2026 $198,700$298,100 / year

At a glance

AI generated

TL;DR

As a senior CPU Physical Design CAD engineer at Qualcomm Technologies in San Diego, Santa Clara, or Austin, you will join the NUVIA team to develop and support cutting-edge place-and-route CAD flows for high-performance custom CPUs. Your daily tasks include integrating new features into existing tools, recommending methodology improvements, and resolving project-specific issues with worldwide design teams. You will work closely with EDA vendors to enhance tool functionality and ensure class-leading power, performance, and area (PPA). Ideal candidates have over ten years of experience in place-and-route for high-performance chips, proficiency in Tcl and Python, and a deep understanding of digital design and physical verification. Experience with Cadence Innovus and advanced technology nodes is essential, as you will leverage your expertise to solve complex problems and collaborate on the full lifecycle of CPU designs from concept to validation.

Skills

Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD

What you'll do

  • Develop and integrate new features in high-performance place-and-route CAD flow.
  • Recommend and implement methodology improvements for optimal power, performance, and area.
  • Maintain, debug, and resolve issues within implementation flows to ensure project success.
  • Provide guidance on tools and methodologies to worldwide CPU physical design teams.
  • Collaborate with EDA vendors to define roadmaps and address tool-related challenges.

What we're looking for

  • Ten+ years of hands-on experience in place-and-route of high-performance chips
  • Proficiency in Tcl and Python for automation and scripting
  • Experience with advanced technology nodes (5nm or lower)
  • Solid understanding of digital design, timing analysis, and physical verification
  • Strong user of industry-standard place-and-route tools like Cadence Innovus
  • Proven ability to manage and regress place-and-route flows
  • Collaborative work with cross-functional teams on complex CPU designs

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $248k
$125k most similar roles pay here $317k

This role pays more than 91% of similar roles. Most pay $168,250–$216,250 — the shaded band above. At the midpoint, this role pays about $248k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 595 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 540 roles with salary data.

Most-posted roles

View all roles at Qualcomm

More like this

Similar roles

CPU Integration CAD Engineer

Qualcomm

Santa Clara, CA 26 days ago $167,100$250,700
Python Tcl Innovus Calibre Docker CI/CD Git Unix/Linux Perl C++ VLSI Physical_Design EDA Advanced_Technology_Nodes Place_and_Route Timing_Sign-off PDV_Analysis

CPU Synthesis CAD Engineer

Qualcomm

Santa Clara, CA 26 days ago $198,700$298,100
Tcl Python Cadence_Genus Synopsys_Fusion_Compiler LEC UPF 5nm_technology_nodes logic_synthesis physical_synthesis EDA_vendors high_performance_chips automation front_end_tasks synthesis_flows computer_architecture micro_architecture circuit_design physical_design

CPU Software Architecture Sr. Staff Engineer

Qualcomm

San Diego, CA 111 days ago $162,600$244,000
C C++ ARM RISC-V RTOS J-TAG ICE SPI I2C PCIe CAN Ethernet USB UFS GIC PLIC Linux_kernel Firmware_development Driver_development Multi-core_CPUs Memory_consistency Messaging_systems Virtualization Security Super_Scalar_Architectures

VLSI Design Engineer for Server / Data Center Products

Qualcomm

San Diego, CA 26 days ago $140,000$210,000
Verilog SystemVerilog VHDL Python Perl TCL Linux Cadence Synopsys ASIC FPGA RTL Design PCIe DDR CXL MIPI USB SMPTE2110 AMBA4 AXI AI Machine Learning High Performance Compute

Hardware Staff Engineer

Qualcomm

San Diego, CA 53 days ago $134,800$202,200
Schematic capture Simulation tools Oscilloscopes Logic analyzers Protocol analyzers High-speed digital design Power delivery design Mixed-signal circuit design EMC testing Automotive reliability standards Thermal management Signal integrity analysis Power integrity analysis PCB layout collaboration CI/CD

CPU Physical Design Engineer (San Diego)

Qualcomm

San Diego, CA 13 days ago $122,500$183,700
Verilog RTL Synthesis Place_and_Route Timing_Analysis Power_Analysis GDS CPU_Microarchitecture Library_Cells High_Performance_Implementation Low_Power_Implementation Tapeout_Flows