Browse tech roles

Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT +20 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

Python Tcl ML Frameworks Physical Design P&R Timing Analysis IR/Signal-EM Power and Noise Analysis Back-end Verification Chip Floorplan Power and Clock Distribution PPA +7 more Show less

Physical Design ASIC Design Flow Synthesis Place and Route Clock Tree Synthesis floor planning TCL Perl Shell Python DFM Signal Integrity FinFET +8 more Show less

Physical Design Synthesis place-and-route Timing Closure Signoff Python TCL Shell Perl ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC Calibre ICV DRC LVS DTCO +15 more Show less

GPU Physical Design SoC Design Synthesis place-and-route Clock Tree Synthesis Timing Closure Signoff STA DRC LVS Python Tcl Shell Perl ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC DTCO +16 more Show less

GPU Physical Design Place-and-Route Floorplanning Timing Closure STA Power-Grid Design DRC LVS FusionCompiler Innovus ICC2 PrimeTime Tempus StarRC RedHawk Python Tcl Shell Perl DTCO PPA Physical Verification Clock Tree Synthesis Synthesis +19 more Show less

VLSI Physical Design P&R Timing Closure Static Timing Analysis IR Drop Analysis Physical Verification RC Extraction Python Perl Tcl Make Synopsys (ICC2 Cadence (Innovus Mentor Graphics ASIC Power Distribution Clock Distribution +12 more Show less

RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks +14 more Show less

Physical Design Static Timing Analysis Signal Integrity EMIR Python Perl Tcl Cadence Innovus Synopsys ICC2 Fusion Compiler PrimeTime Tempus PNR Low-Power Design PPA IR Drop +11 more Show less

CPU Architecture RTL Physical Design VLSI Circuit Design Power Delivery Power Gating Thermal Throttling Advanced Packaging SoC Design Process Technology High-Frequency Design Power Management +8 more Show less

Tcl Python Cadence Innovus Place-and-Route Physical Design Timing Analysis Physical Verification Digital Design Automation PPA 5nm Hardware Engineering +7 more Show less

Physical Design Innovus Primetime Voltus Tcl Python Perl Synopsys ICC Cadence Floorplanning Place and Route Timing Closure DRC EMIR Physical Verification +10 more Show less

Cadence-Innovus TCL Python Physical Design Place and Route STA Power Gating Clock Gating floor planning Design for Yield +5 more Show less

PnR STA Tcl Shell Scripting DRC LVS Physical Design IR Drop Electromigration Gate-level Patching CAD Utilities +6 more Show less

Physical Design PnR STA TCL Shell Scripting DRC LVS CTS GDS2 Netlist IR Drop Electromigration EDA Tools +8 more Show less

VLSI Python C++ EDA AI ML LLMs Interposer Design Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design +10 more Show less

Physical Design Static Timing Analysis Logic Synthesis Floorplanning clock-tree synthesis Routing ECO RTL Python Tcl Perl Make AI ML DL LLMs EDA Tools Signoff IR Drop Xtalk +15 more Show less

Physical Design Spice Clock Architecture Clock Distribution DRC LVS Signal Integrity Routing Process Technology Excel +5 more Show less