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ASIC Verilog SystemC Python Perl C++ Linux Git JIRA Confluence CI/CD +6 more Show less

Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools +13 more Show less

Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ TCL UVM DVFlow CI/CD Linux Git SVN DOCSIS Moore's Law Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler Synopsys PrimeTime Qualcomm SNAP EDA Suite +15 more Show less

Python TCL Perl Verilog VHDL Calibre ICC2 PrimeTime PT QuestaSim DC Synopsys Cadence MentorGraphics Linux Git CI/CD Docker Kubernetes +14 more Show less

Verilog SystemC Python Perl C++ Linux Git SVN JIRA Confluence CI/CD Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler +14 more Show less

Tcl Python Perl Innovus Fusion Compiler PrimeTime Calibre DRC LVS ERC STA AI/ML Terraform CI/CD Kubernetes Git Jenkins PostgreSQL AWS +14 more Show less

Python Tapeout Physical Verification Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC Design-for-Manufacturing Design-for-Yield SOC Algorithm Design Micro-Architecture CI/CD +10 more Show less

C++ Python Tcl Perl Shell VCS DC PT PrimeTime ICC2 Calibre OpenAccess Verilog SystemVerilog Linux Git CI/CD Docker +13 more Show less

Python Tapeout DRC LVS Design-for-Manufacturing Design-for-Yield Place_and_Route Clock_Tree_Synthesis Floor_Planning PDN Timing_analysis CI/CD Kubernetes AWS Git SVN Linux +12 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl UPF CPF SDC CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less

TCL PERL EDA Tools RF Verification RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +7 more Show less

TCL PERL EDA Tools RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +6 more Show less

Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD +5 more Show less

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Physical Design Convergence Power Integrity Analysis Custom Clock Design AI Tools +10 more Show less

Verilog RTL Synthesis Place & Route Timing Analysis Power Analysis GDS Library Cells High Performance Design Low Power Design Tapeout Flows +6 more Show less

SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clock_Tree_Synthesis HDL Verilog SystemVerilog Cadence Synopsys Calibre +15 more Show less

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment +14 more Show less

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment +14 more Show less

Python Tcl Docker OpenAI APIs Pinecone Weaviate Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus MCP-based wrapper layer RTL2GDSII flow ML-driven PnR EDA tools +12 more Show less