Senior ASIC Physical Design Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$165,000–$241,400 / yr
Posted
11 days ago
Closes
Aug 1, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $203k
$135k most similar roles pay here $253k

This role pays more than 62% of similar roles. Most pay $173,850–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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View all roles at Cisco

At a glance

TL;DR · Senior ASIC Physical Design Engineer

Role Posting Log in to save

As a Physical Design Engineer at Cisco, you will join the high-performance networking chip design team and take on a critical role in the RTL-to-GDSII implementation flow for advanced semiconductor nodes from sub-16nm to 3nm. Your responsibilities include driving hierarchical floor planning, place and route strategies, clock distribution, power integrity analysis, and timing convergence while collaborating with various teams to ensure efficient backend design flows. You will perform static timing analysis, develop automated scripts within STA tools, manage timing ECO strategies using Tweaker/PrimeTime, and recommend improvements for tool and methodology efficiency. The ideal candidate has extensive experience with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, and proficiency in Python along with AI integration skills to enhance design accuracy and efficiency.

Skills

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Physical Design Convergence Power Integrity Analysis Custom Clock Design AI Tools

What you'll do

  • Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
  • Define and execute hierarchical floor planning, place and route strategies.
  • Perform static timing analysis (STA) and develop automated scripts within STA tools.
  • Implement and manage timing ECO strategies using Tweaker/PrimeTime.
  • Analyze quality gaps and recommend tool, flow, and methodology improvements.

What we're looking for

  • Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC experience.
  • Experience with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, and Calibre/Pegasus.
  • Proficiency in fullchip activities including floor-planning, power-grid planning, partitioning, and pin-assignment.
  • Expertise in hierarchical design, timing closure, physical design convergence, and power integrity analysis.
  • Strong skills in static timing analysis, defining timing constraints, and custom clock design at chip level.

Related searches

More Senior ASIC Physical Design Engineer jobs Senior ASIC Physical Design Engineer jobs in San Jose Remote Senior ASIC Physical Design Engineer jobs All jobs at Cisco

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