Physical Design Timing Engineer (STA)

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$141,300–$226,000 / yr
Posted
15 days ago
Closes
Nov 1, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k
This role $184k
$127k most similar roles pay here $237k

This role pays more than 55% of similar roles. Most pay $156,000–$213,743 — the shaded band above. At the midpoint, this role pays about $184k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Physical Design Timing Engineer (STA)

Apply Now Log in to save

The Full Chip Static Timing Analysis (STA) Engineer at the semiconductor design team is an experienced professional responsible for ensuring ASIC performance targets are met across all operating conditions. This role involves full-chip timing sign-off, constraint development, advanced timing analysis including On-Chip Variation and Signal Integrity, and managing hundreds of timing scenarios through Multi-Mode Multi-Corner (MMMC) Analysis. The engineer will automate ECOs to resolve setup, hold, and transition violations, collaborate with cross-functional teams like RTL, Physical Design, and DFT, and document best practices for continuous improvement. Proficiency in Tcl, Python, Perl, Cadence or Synopsys tools, and scripting languages is essential, along with strong problem-solving skills and clear communication.

Skills

Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools

What you'll do

  • Own the final timing closure for ASIC, performing quality checks across all PVT corners.
  • Author, validate, and maintain SDC constraints for various modes including functional and test modes.
  • Manage hundreds of timing scenarios to ensure reliability across diverse operating environments.
  • Automate and implement ECOs to fix setup, hold, and transition violations in the design cycle.
  • Script analysis flows and data mining using Tcl, Python, and Perl.

What we're looking for

  • Minimum 12 years of hands-on experience in ASIC STA and timing constraints development.
  • Expert proficiency in Cadence or Synopsys tools for timing closure.
  • Deep knowledge of advanced timing concepts like AOCV/POCV, signal integrity, and IR-drop aware STA.
  • High proficiency in scripting languages such as Tcl, Python, and Perl.
  • Experience managing multi-mode multi-corner (MMMC) analysis to ensure reliability across diverse operating environments.
  • Strong problem-solving skills with attention to technical details.
  • EDA tool expertise and ability to document best practices for continuous improvement.

Related searches

More Physical Design Timing Engineer jobs Physical Design Timing Engineer jobs in San Jose All jobs at Broadcom

More like this

Similar roles

Careers

Qualcomm

Santa Clara, CA 5 days ago
TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS TCL scripting Perl scripting Python scripting ASIC back-end design flows Cross-talk noise Signal Integrity Layout Parasitic Extraction Feed through handling
Save

CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 99 days ago $198,700–$298,100
TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction
Save

Physical Design Engineer

Broadcom

San Jose, CA 108 days ago $141,300–$226,000
Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration
Save

Physical Design Engineer

Broadcom

San Jose, CA 40 days ago $120,000–$192,000
Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter
Save

Timing Design Engineer

Apple Inc

San Diego, CA 45 days ago $120,300–$210,100
Verilog SystemC VHDL Cadence Synopsys Tensilica Mentor Graphics ModelSim Python Git JIRA Confluence CI/CD
Save