Physical Design Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
Austin, TX
Salary
$137,000–$200,500 / yr
Posted
4 days ago
Closes
Jul 31, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $172k
This role $169k
$120k most similar roles pay here $214k

This role pays more than 50% of similar roles. Most pay $139,000–$205,000 — the shaded band above. At the midpoint, this role pays about $169k versus about $172k for comparable roles.

Based on 239 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 179 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 179 roles with salary data.

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View all roles at Cisco

At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer at Cisco, you will join the high-performance networking chip team and take on a critical role in the RTL-to-GDSII implementation flow for advanced semiconductor nodes from sub-16nm to 3nm. Your daily responsibilities include driving hierarchical floor planning, place and route strategies, managing clock and power distribution, and executing timing convergence techniques. You will perform static timing analysis, develop automated scripts within STA tools, implement ECO strategies using Tweaker/PrimeTime, and collaborate with RTL, DFT, and EDA vendors to enhance design efficiency. The ideal candidate has extensive experience in advanced node tapeouts and proficiency with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, and Calibre/Pegasus, along with a strong background in hierarchical design, timing closure, and power integrity analysis.

Skills

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment

What you'll do

  • Own and drive RTL-to-GDSII implementation for advanced semiconductor nodes.
  • Define and execute hierarchical floor planning and place-and-route strategies.
  • Perform static timing analysis and develop automated scripts within STA tools.
  • Implement and manage timing ECO strategies using Tweaker/PrimeTime tools.
  • Analyze backend design flows to recommend tool, flow, and methodology improvements.

What we're looking for

  • Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC Design experience.
  • Experience with RTL-to-GDSII flow and design tapeouts in advanced process technologies (7nm/5nm/3nm).
  • Proficiency in EDA tools such as Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus.
  • Expertise in fullchip activities including floor-planning, power-grid planning, partitioning, and pin-assignment.
  • Strong background in hierarchical design, timing closure, physical design convergence, and power integrity analysis.
  • Knowledge of static timing analysis, defining timing constraints, corners/voltage definitions, and custom clock designs.
  • Experience with Python scripting and AI tools for accurate prompts.

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