Physical IC Design Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Posted: 9 days ago
Closes: Dec 16, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k

This role $187k

$132k most similar roles pay here $240k

This role pays more than 55% of similar roles. Most pay $153,100–$213,375 — the shaded band above. At the midpoint, this role pays about $187k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 98 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 95 roles with salary data.

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At a glance

TL;DR · Physical IC Design Engineer

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Broadcom seeks a Physical IC Design Engineer with extensive experience to join its Asic Products Division, focusing on advancing Artificial Intelligence and Machine Learning ecosystems through PCIe Switch Products and enhancing Enterprise Storage Products. This role involves executing physical design tasks such as synthesis, verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floor-planning, and layout development while collaborating closely with RTL engineers to ensure world-class performance in mega datacenters. The ideal candidate will possess expertise in TCL/PERL scripting, proficiency in EDA tools, and a full physical design cycle experience from RTL to tape-out, along with strong communication skills.

Skills

TCL PERL EDA Tools RF Verification RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development

What you'll do

Execute Physical Design, Synthesis, and Timing Closure for ASIC projects.
Perform EM/IR Analysis to ensure reliable chip performance.
Develop and refine physical design flow and methodology.
Collaborate with RTL Engineers on IC design aspects.
Conduct Place and Route operations for efficient chip layout.

What we're looking for

At least 12 years of experience in Physical IC Design.
Expertise in executing physical design, synthesis, verification, and timing closure.
Proficiency in TCL/Perl scripting and EDA tools for RTL to tape-out cycle.
Experience with EM/IR analysis, place and route, clock tree synthesis, floor-planning, and layout.
Ability to develop flow and methodology in Physical IC Design.
Strong collaboration skills with IC design RTL engineers.

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