Staff SOC Physical Design Engineer

Qualcomm

Hybrid

Quick summary

Work type
Hybrid
Location
San Diego, CA
Salary
$154,742–$210,000 / yr
Posted
3 days ago
Closes
Dec 22, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $184k
This role $182k
$132k most similar roles pay here $230k

This role pays more than 52% of similar roles. Most pay $158,188–$208,975 — the shaded band above. At the midpoint, this role pays about $182k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Staff SOC Physical Design Engineer

Role Posting Log in to save

The Senior Physical Design Engineer role at Qualcomm Technologies, Inc. involves leading the physical design flow for high-speed DDR and graphics systems on chip (SoC), focusing on power optimization and performance. This position requires expertise in floor planning, clock tree synthesis, place and route, power distribution network (PDN) analysis, timing closure, and various verification checks such as LVS, DRC, and yield optimization. The ideal candidate will work closely with cross-functional teams to ensure signoff for tapeout, using advanced tools like Cadence Innovus, Synopsys IC Compiler, and Calibre for physical verification. Strong skills in scripting languages like Python are essential for automation and debugging complex designs. This role demands a deep understanding of semiconductor design challenges at the cutting edge of technology.

Skills

Python TCL Perl Verilog VHDL Calibre ICC2 PrimeTime PT QuestaSim DC Synopsys Cadence MentorGraphics Linux Git CI/CD Docker Kubernetes

What you'll do

  • Leads and plans the physical design flow for high-speed DDR and graphics.
  • Synthesizes ambiguous requirements to optimize power utilization in SOC products.
  • Performs complex responsibilities including floor planning and clock tree synthesis.
  • Conducts place and route, PDN, and timing analysis for chip-level optimization.
  • Executes various physical verification checks at both chip and block levels.
  • Provides schedules and supports cross-functional engineering efforts for signoff.

What we're looking for

  • At least 7 years of experience in physical design flow for high-speed DDR and graphics.
  • Expertise in floor planning, clock tree synthesis, place and route, PDN, and timing analysis.
  • Proficient in performing LVS, DRC, and other physical verification checks at chip/block levels.
  • Strong background in power utilization optimization for system-on-chip (SoC) products.
  • Experience leading cross-functional engineering efforts to achieve signoff closure for tapeout.

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