Staff ASICS Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$154,742–$210,000 / yr
Posted
6 days ago
Closes
Dec 19, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $182k
$138k most similar roles pay here $235k

This role pays less than 56% of similar roles. Most pay $168,687–$213,543 — the shaded band above. At the midpoint, this role pays about $182k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Staff ASICS Physical Design Engineer

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As a Staff ASICS Physical Design Engineer at Qualcomm Technologies, Inc., you will lead the timing analysis of complex sub-systems from SoC context, ensuring timing closure across various operating modes and technology nodes such as 14nm, 5nm, 3nm, and beyond. Your daily tasks include synthesizing ambiguous requirements, performing constraint validation, conducting clock tree analyses, developing flow/scripts for easy access to timing reports, mentoring junior team members, and generating ECOs for subsystems. You will work with advanced design methodologies and timing signoff processes, collaborating closely with multiple teams to ensure accurate correlation between PNR tool and timing signoff tools. This role requires expertise in C++, assembly language, algorithms, and automation, as well as a strong background in electrical or computer engineering, ideally from previous roles like Design Verification Engineer or Physical Design Engineer.

Skills

C++ Python Tcl Perl Shell VCS DC PT PrimeTime ICC2 Calibre OpenAccess Verilog SystemVerilog Linux Git CI/CD Docker

What you'll do

  • Conduct timing analysis of complex sub-systems from SoC context.
  • Ensure timing closure across various operating modes and technology nodes.
  • Develop multiple flow/scripts for easy access to timing reports.
  • Mentor junior team members in design methodologies and timing signoff processes.
  • Perform correlation activities between PNR tool and timing signoff tools.
  • Generate ECOs for various subsystems to address timing issues.
  • Plan pipelines early for critical interface timing closure.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and at least 7 years of relevant experience.
  • Expertise in timing analysis for complex sub-systems on advanced technology nodes like 14nm, 5nm, 3nm.
  • Proficiency in SoC design architecture, methodologies, and timing signoff processes.
  • Experience in constraint validation, clock tree synthesis, and pipeline planning for critical interfaces.
  • Development of flow/scripts to facilitate access to timing reports and correlation between PNR and timing signoff tools.
  • Mentorship and training of junior team members, participation in design reviews, and implementation of development plans.

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