Staff SOC Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Posted
6 days ago
Closes
Dec 19, 2026
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $184k
$132k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $158,450–$208,975.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Staff SOC Physical Design Engineer

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As a Staff SOC Physical Design Engineer at Qualcomm Technologies, Inc., you will lead the physical design flow for high-speed DDR and graphics systems, focusing on optimizing power utilization and performance. Your daily tasks include floor planning, clock tree synthesis, place and route operations, PDN creation, timing analysis, and conducting various physical verification checks such as LVS and DRC at both chip and block levels. You will collaborate closely with cross-functional teams to ensure signoff closure for tapeout and contribute effectively in design reviews and project meetings. The role requires expertise in electrical engineering or a related field, along with extensive experience in SOC algorithm design, micro-architecture, and physical verification flows. Key skills include debugging, automation, and algorithms, while proficiency in tools like Cadence, Synopsys, and Mentor Graphics is essential.

Skills

Python Tapeout DRC LVS Design-for-Manufacturing Design-for-Yield Place_and_Route Clock_Tree_Synthesis Floor_Planning PDN Timing_analysis CI/CD Kubernetes AWS Git SVN Linux

What you'll do

  • Leads and plans the physical design flow for high-speed DDR and graphics in SoCs.
  • Synthesizes ambiguous requirements to optimize power utilization and performance.
  • Conducts floor planning, clock tree synthesis, place and route, PDN, and timing analysis.
  • Executes physical verification checks like LVS, DRC at chip and block levels.
  • Supports cross-functional teams to achieve signoff closure for tapeout.

What we're looking for

  • Master's degree in Electrical/Electronic engineering or related field and 3 years of experience.
  • Bachelor's degree in Electrical/Electronic engineering or related field and 7 years of progressive experience.
  • Expertise in Physical Design Flow, including floor planning, clock tree synthesis, place and route, PDN, timing analysis.
  • Proficiency in performing physical verification checks such as LVS, DRC, design-for-manufacturing & yield.
  • Strong contributor at design reviews and project meetings with ability to communicate complex technical issues effectively.

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