Staff SOC Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$161,179–$210,000 / yr
Posted
4 days ago
Closes
Dec 21, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $184k
This role $186k
$132k most similar roles pay here $230k

This role pays more than 55% of similar roles. Most pay $158,188–$208,975 — the shaded band above. At the midpoint, this role pays about $186k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Staff SOC Physical Design Engineer

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The Senior Lead Engineer role at Qualcomm Technologies focuses on leading the physical design flow for high-speed DDR and graphics systems-on-chip (SoCs), emphasizing power optimization and performance. This position involves complex responsibilities such as floor planning, clock tree synthesis, place and route operations, power distribution network management, timing analysis, and various physical verification checks. The ideal candidate will work closely with cross-functional teams to ensure signoff closure for tapeout, driving the design process from initial requirements through final verification. Required skills include expertise in tools like Cadence, Synopsys, and Mentor Graphics, proficiency in scripting languages such as Python or Perl, and a strong background in electrical engineering or computer science. Experience with large-scale SoC designs is essential, particularly in areas related to high-speed interfaces and power-efficient micro-architecture.

Skills

Python Tapeout Physical Verification Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC Design-for-Manufacturing Design-for-Yield SOC Algorithm Design Micro-Architecture CI/CD

What you'll do

  • Leads and plans the physical design flow for high-speed DDR and graphics.
  • Synthesizes ambiguous requirements to optimize power utilization in SoC products.
  • Conducts floor planning, clock tree synthesis, place and route operations.
  • Designs power distribution networks (PDN) and performs timing analysis.
  • Executes physical verification checks including LVS, DRC at chip/block levels.
  • Supports cross-functional engineering teams to achieve tapeout signoff closure.

What we're looking for

  • 7+ years of experience in physical design flow for high-speed DDR and graphics.
  • Expertise in floor planning, clock tree synthesis, place and route, PDN, timing analysis.
  • Proficiency in performing LVS, DRC, and other physical verification checks at chip/block levels.
  • Strong background in SOC algorithm design, modeling, and methodology focusing on power optimization.
  • Experience leading cross-functional engineering teams to drive signoff closure for tapeout projects.

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