Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$107,400–$161,200 / yr
Posted
3 days ago
Closes
Dec 22, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $168k
This role $134k
$96k most similar roles pay here $211k

This role pays less than 76% of similar roles. Most pay $135,836–$199,407 — the shaded band above. At the midpoint, this role pays about $134k versus about $168k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 828 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 508 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Physical Design Engineer

Join the dynamic and innovative team at Qualcomm Technologies as a Senior ASIC Design Engineer, where you will play a pivotal role in developing cutting-edge semiconductor solutions for mobile devices and beyond. Your primary responsibilities include designing, verifying, validating, and integrating complex ASICs to ensure they meet stringent performance and reliability standards. You will collaborate closely with cross-functional teams to define system requirements, develop detailed design specifications, and implement robust verification methodologies. Proficiency in languages such as SystemVerilog, VHDL, and C++, along with expertise in tools like Cadence Genus, Synopsys DC, and Mentor Calibre, is essential. This role demands a deep understanding of digital logic design principles and the ability to work effectively on large-scale projects that impact millions of users globally.

What you'll do

  • Design and implement complex digital circuits for ASICs.
  • Develop test plans and perform verification on integrated circuit designs.
  • Optimize chip performance through detailed analysis and simulation.
  • Collaborate with cross-functional teams to integrate hardware components.
  • Troubleshoot and resolve issues in the validation phase of ASIC development.

What we're looking for

  • 3+ years of experience in ASIC design, verification, validation, or integration.
  • Strong background in hardware and software co-design and system-level testing.
  • Proficiency in scripting languages for automation and debugging.
  • Experience with industry-standard EDA tools and methodologies.
  • Excellent problem-solving skills and ability to work in a team environment.

More like this

Similar roles

Physical Design Engineer

Qualcomm

San Diego, CA 31 days ago $98,500$147,700
Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ Tcl Unix/Linux Cadence Synopsys ModelSim Xilinx Vivado Git JIRA Confluence CI/CD

R&D Engineer, Physical Design

Broadcom

San Jose, CA 19 days ago $143,800$230,000
Verilog VHDL Cadence Virtuoso Synopsys IC Compiler Calibre TritonRoute Mentor Graphics Calibre Python Perl UNIX/Linux Git SVN JIRA Confluence CI/CD

Careers at Qualcomm

Qualcomm

Austin, TX 2 days ago $164,000$246,000
Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ TCL UVM DVFlow CI/CD Linux Git SVN DOCSIS Moore's Law Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler Synopsys PrimeTime Qualcomm SNAP EDA Suite

Physical Design Engineer

Broadcom

San Jose, CA 19 days ago $141,300$226,000
Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration

Physical Design Engineer

Cisco

Remote (San Jose, CA) 16 days ago $165,000$241,400
Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment
Remote