Senior HW SOC/ASIC Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
7 days ago
Closes
Dec 18, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k
This role $144k
$103k most similar roles pay here $231k

This role pays less than 85% of similar roles. Most pay $158,750–$212,500 — the shaded band above. At the midpoint, this role pays about $144k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Senior HW SOC/ASIC Physical Design Engineer

Role Posting Log in to save

Join our dynamic team at Qualcomm Technologies as a Physical Design Engineer, where you will play a pivotal role in the RTL-to-GDSII flow, focusing on floor-planning, clock tree synthesis (CTS), place-n-route (PnR), and timing closure to ensure robust, low-skew, power-efficient designs. Your daily tasks include executing CTS using tools like Innovus and ICC2, driving STA with PrimeTime, optimizing for PPA, and conducting formal equivalence checks between RTL and netlist. You will also collaborate closely with backend teams for tapeout preparation, support physical verification, and customize reference flows to align with project needs. Essential skills include expertise in EDA tools, scripting languages like TCL, Python, and Perl, and a strong background in advanced node technologies such as 7nm, 5nm, and 3nm FinFETs. This role demands proficiency in low-power design techniques and the ability to interface effectively with foundries and EDA vendors to ensure compliance with latest DRMs and tapeout checklists.

Skills

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso

What you'll do

  • Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools.
  • Drive timing closure across multiple corners and modes using static timing analysis (STA) tools.
  • Optimize design for power, performance, and area (PPA).
  • Conduct formal equivalence checks between RTL and netlist.
  • Support physical verification including DRC, LVS, ERC, antenna, and density checks.
  • Customize and optimize reference physical verification flows to align with project needs and foundry requirements.
  • Perform GDS-to-GDS comparisons to validate ECO changes and ensure layout integrity.

What we're looking for

  • 3+ years of experience in physical design with focus on clock tree implementation.
  • Strong understanding of digital timing concepts and synchronous/asynchronous design principles.
  • Proficiency with EDA tools for CTS, STA, and physical verification (ICC2, Innovus, PrimeTime).
  • Experience with advanced nodes (7nm, 5nm, 3nm) and FinFET technologies.
  • Solid scripting skills in TCL, Python, Perl for flow automation and data analysis.
  • Familiarity with low-power design techniques including clock gating and multi-voltage domains.

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