Director, Physical Design & CAD Methodology, ASIC/SoC

Cisco

Closes tomorrow Remote

Quick summary

Work type: Remote
Location: Remote
Salary: $230,100–$325,300 / yr
Posted: 4 days ago
Closes: Jun 29, 2026 (soon)

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $278k

$131k most similar roles pay here $346k

This role pays more than 97% of similar roles. Most pay $175,000–$223,700 — the shaded band above. At the midpoint, this role pays about $278k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · Director, Physical Design & CAD Methodology, ASIC/SoC

Role Posting Log in to save

Join the Physical Design Methodology team as a senior leader responsible for defining global design strategies and deploying advanced CAD flows to support high-performance SoC and ASIC designs. You will manage a team of engineers, allocate resources efficiently, and serve as the primary technical liaison with EDA vendors like Synopsys, Cadence, and Siemens. Your daily tasks include evaluating state-of-the-art tools, automating processes through scripting in Tcl, Python, and Perl, and integrating AI/ML features to optimize design performance. You will also collaborate closely with RTL Design, DFT, Architecture, and Physical Implementation teams to ensure seamless integration and tool interoperability while working on cutting-edge process geometries like 7nm, 5nm, and beyond.

Skills

Tcl Python Perl Innovus Fusion Compiler PrimeTime Calibre DRC LVS ERC STA AI/ML Terraform CI/CD Kubernetes Git Jenkins PostgreSQL AWS

What you'll do

Define global physical design methodology strategy for all phases of chip development.
Architect and deploy advanced CAD flows for complex SoC and ASIC designs.
Drive innovation in hierarchical design and multi-die integration methodologies.
Evaluate and select state-of-the-art EDA tools to enhance engineering productivity.
Develop robust scripting infrastructure to automate tasks and ensure flow consistency.
Negotiate tool licensing requirements and manage the CAD budget effectively.
Collaborate with external foundries to integrate PDKs and resolve deep sub-micron effects.

What we're looking for

Master’s or Ph.D. in Electrical/Computer Engineering with 10+ years of ASIC/SoC physical design experience.
5+ years of leadership experience managing CAD and physical design teams.
Expertise in advanced process geometries (7nm, 5nm, 3nm).
Proficiency in full RTL-to-GDSII design flows including verification and sign-off processes.
Strong knowledge of EDA tool suites for physical design and verification.
Experience with hierarchical design, multi-die integration, and AI/ML-driven EDA features.

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