HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff (US Citizenship Required)

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
7 days ago
Closes
Dec 18, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $175k
$130k most similar roles pay here $230k

This role pays less than 62% of similar roles. Most pay $162,480–$212,500 — the shaded band above. At the midpoint, this role pays about $175k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff (US Citizenship Required)

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Join Qualcomm Technologies as a Physical Design Engineer where you will play a pivotal role in the RTL-to-GDSII flow, focusing on floor-planning, clock tree synthesis (CTS), and place-and-route (PnR) activities to ensure timing closure across multiple corners and modes. Your daily tasks include executing CTS using tools like Innovus and ICC2, collaborating with RTL designers to resolve design issues, optimizing designs for power, performance, and area (PPA), and conducting formal equivalence checks between RTL and netlist. You will also support physical verification processes, develop automation scripts in TCL, Python, or Perl, and work closely with backend teams for tapeout preparation. With experience in advanced nodes like 7nm and 5nm, you should be proficient in EDA tools such as PrimeTime and Calibre, and have a strong grasp of low-power design techniques including clock gating and multi-voltage domains.

Skills

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl UPF CPF SDC CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso

What you'll do

  • Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools.
  • Drive timing closure across multiple corners and modes using static timing analysis (STA) tools.
  • Optimize design for power, performance, and area (PPA).
  • Conduct formal equivalence checks between RTL and netlist.
  • Support physical verification including DRC, LVS, antenna checks, and GDS-to-GDS comparisons.
  • Customize and optimize reference physical verification flows to align with project needs and foundry requirements.

What we're looking for

  • 4+ years of experience in physical design with a focus on clock tree design and implementation.
  • Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.
  • Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime).
  • Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
  • Solid scripting skills in TCL, Python, Perl for flow automation and data analysis.
  • Familiarity with low-power design techniques including clock gating and multi-voltage domains.

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