Staff Physical Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
2 days ago
Closes
Dec 23, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $175k
$129k most similar roles pay here $241k

This role pays less than 59% of similar roles. Most pay $161,450–$222,000 — the shaded band above. At the midpoint, this role pays about $175k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Staff Physical Design Engineer

Role Posting Log in to save

As a Senior ASIC Design Engineer at Qualcomm Technologies, you will join the cutting-edge semiconductor team to develop advanced integrated circuits for mobile and computing devices. Your primary responsibilities include designing, verifying, validating, and integrating complex ASICs, ensuring they meet performance and power efficiency targets. You will work closely with cross-functional teams to define specifications, create detailed design documentation, and collaborate on silicon validation efforts. Proficiency in Verilog or SystemVerilog, along with experience in scripting languages like Python or Perl for automation tasks, is essential. Familiarity with industry-standard EDA tools such as Cadence or Synopsys will also be beneficial. This role involves tackling intricate challenges at a large scale, contributing to the development of innovative products that power global technology ecosystems.

Skills

ASIC Verilog SystemC Python Perl C++ Linux Git JIRA Confluence CI/CD

What you'll do

  • Design and implement complex ASIC circuits for semiconductor products.
  • Develop test plans and perform rigorous verification to ensure design integrity.
  • Collaborate on integration efforts to merge multiple components into a cohesive system.
  • Optimize power consumption and performance of integrated circuits during validation.
  • Troubleshoot and resolve issues in chip designs through detailed analysis.

What we're looking for

  • At least 3 years of experience in ASIC design, verification, validation, or integration.
  • Strong background in semiconductor technology and chip development processes.
  • Proficiency in relevant tools and software for ASIC design and testing.
  • Experience with hardware description languages such as Verilog or SystemVerilog.
  • Knowledge of digital and mixed-signal circuit design principles.

Related searches

More Staff. Physical Design Engineer jobs Staff. Physical Design Engineer jobs in San Diego All jobs at Qualcomm

More like this

Similar roles

Physical Design Engineer

Qualcomm

Santa Clara, CA 3 days ago $107,400–$161,200
Verilog SystemC Python Perl C++ Linux Git SVN JIRA Confluence CI/CD Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler
Save

Physical Design Engineer

Qualcomm

San Diego, CA 31 days ago $98,500–$147,700
Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ Tcl Unix/Linux Cadence Synopsys ModelSim Xilinx Vivado Git JIRA Confluence CI/CD
Save

Staff Engineer

Qualcomm

San Diego, CA 26 days ago $158,400–$237,600
C++ Python Linux Android QNX Machine Learning AI Models Hardware Architecture Compiler Tools Model Efficiency Tools Inference Solutions Training Solutions Experimentation Evaluation Techniques
Save

Senior Staff Physical Design Feasibility Engineer

Samsung Electronics

Remote 18 days ago $180,200–$270,400
Perl TCL Shell Python Verilog GPU architecture SOC/ASIC design flow P&R tools Floor-planning PPA optimization Logical equivalence checking Timing constraints Scripting Programming
Remote
Save

Physical Design Engineer

Broadcom

San Jose, CA 19 days ago $141,300–$226,000
Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration
Save

Physical Design Engineer

Cisco

Remote (San Jose, CA) 16 days ago $165,000–$241,400
Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment
Remote
Save