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Python C++ Perl Matlab Visual_Studio_Code Analog_Mixed_Signal_Modeling Simulation Verification Design_for_Test CI/CD Azure Git Docker Jenkins PostgreSQL MariaDB +11 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators microarchitecture computer architecture RTL debugging scripting languages +9 more Show less

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

UVM SystemVerilog C++ Python Perl SoC IP verification FPGA emulation platforms AI accelerators Mentoring Debugging RTL Microarchitecture Computer architecture +10 more Show less

SystemVerilog UVM SVA Questa VCS Xcelium Git Linux Python Tcl Makefile SVUnit Formal verification CDC verification CI/CD Nix DO-254 +12 more Show less

C++ Python Go CI/CD UART CANbus SITL HITL V&V Embedded Linux RTOS Bare-metal Development Test Automation Scripting +9 more Show less

MIL-STD-810 MIL-STD-461 MIL-STD-704 V&V planning Qualification by Similarity (QBS) requirements management tools Microsoft Office Foundry Confluence DO-160 MIL-HDBK-310 AS9100 +7 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Python ASIC Verification Design CI/CD

Python ASIC Verification CI/CD

Python ASIC Verification CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

Python ASIC verification FPGA verification