Mixed-Signal Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $255k

$124k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Mixed-Signal Verification Engineer

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The Mixed-Signal Verification Engineer joins the wireless silicon development team to support the design of highly energy-efficient wireless SOCs. In this role, you will verify RF and mixed-signal blocks and their interfaces, ensuring silicon-correct functionality and optimal coverage. Your daily responsibilities include reviewing specifications, defining verification plans, and developing top and block-level testbenches. You will build and reuse monitors and checkers, debug failures, manage bug tracking, and write scripts for flow automation. Key technical requirements include expertise in SystemVerilog, UVM methodology, and HDL. You must also possess experience with UPF, Python, Matlab, Virtuoso Composer, ADE, and HED. This position focuses on solving complex mixed-signal verification challenges within the wireless product area to deliver innovative, functional hardware.

Skills

System Verilog UVM Verilog Mixed-Signal Verification RF Python Matlab UPF Virtuoso Composer ADE HED HDL SOC Automation Bug Tracking

What you'll do

Define and execute verification plans by reviewing specifications and extracting key features.
Develop top-level and block-level Mixed Signal and Digital testbenches using the UVM framework.
Build and reuse monitors and checkers for RF and Mixed-Signal blocks.
Debug failures, manage bug tracking, and analyze coverage to ensure silicon-correct functionality.
Write scripts to automate verification flows.
Improve Mixed Signal verification methodologies by implementing novel ideas and leveraging AI.
Create and use real-numbered analog behavioral models in System Verilog.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Industry verification experience with RF/Mixed-Signal blocks and SOCs.
Expertise building Mixed-Signal testbenches, checkers, and tests using System Verilog.
Experience in UVM methodology and HDL (System Verilog, Verilog) for verification.
Strong verification skills in problem solving, testing, and debugging.
Understanding of common analog/RF blocks.
Experience with UPF, Python, or Matlab.
Experience with Virtuoso Composer, ADE, and HED.
Masters or PhD degree in technical disciplines with at least 5+ years of hands-on experience in Mixed-Signal verification (preferred).
Wireless experience (preferred).
Expertise creating and using real-numbered analog behavioral models in System Verilog (preferred).

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