Mixed-Signal Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $206k

This role $168k

$108k $256k

below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $169,625–$241,750 — the blue band above. At the midpoint, this role pays about $168k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Mixed-Signal Verification Engineer

Role Posting Log in to save

Mixed-Signal Verification Engineer The Mixed-Signal Verification Engineer joins the wireless silicon development team to support the wireless SOC organization. This role focuses on the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. The engineer will review specifications, define verification plans, and develop top and block level testbenches. Key responsibilities include building and reusing monitors and checkers, debugging failures, managing bug tracking, and writing scripts for flow automation. The candidate must utilize System Verilog, Verilog, and the UVM framework, while also leveraging Python, Matlab, UPF, Virtuoso Composer, ADE, and HED. The work involves developing best-in-class verification methodologies to ensure silicon-correct functionality and optimal coverage for highly energy-efficient wireless designs and new technologies.

Skills

System Verilog UVM Verilog Mixed-Signal Verification RF Python Matlab UPF Virtuoso Composer ADE HED HDL SOC Automation

What you'll do

Review specifications to extract features and execute comprehensive verification plans.
Develop top-level and block-level Mixed Signal and Digital testbenches using the UVM framework.
Build and reuse monitors and checkers for RF and Mixed-Signal blocks.
Debug failures, manage bug tracking, and analyze coverage to ensure silicon-correct functionality.
Write scripts to automate verification flows.
Improve Mixed Signal verification methodologies by implementing novel ideas and leveraging AI.

What we're looking for

Minimum requirement of a bachelor's degree.
Bachelor degree in technical disciplines with 2+ years of relevant industry experience (preferred).
Industry verification experience with RF/Mixed-Signal blocks and SOCs.
Expertise building Mixed-Signal testbenches, checkers, and tests using System Verilog.
Experience in UVM methodology and HDL (System Verilog, Verilog) for verification.
Strong verification skills in problem solving, testing, and debugging.
Understanding of common analog/RF blocks.
Experience with UPF, Python or Matlab, and Virtuoso Composer, ADE, and HED.
Expertise creating and using real-numbered analog behavioral models in System Verilog (preferred).
Wireless experience (preferred).

Save