Principal Physical Verification Engineer

What you'll do

• Execute chip-level physical verification and resolve complex design issues.
• Set up DRM runsets and tool flows for advanced semiconductor nodes.
• Manage rules for top-level floorplans, I/O, and bump planning.
• Provide technical direction on DRC, LVS, ERC, and PERC verification methodologies.
• Develop best practice guidelines for physical verification flows and runtime optimizations.
• Implement Design for Manufacturability (DFM) fixes including critical area analysis and via-doubling.
• Analyze ESD, latch-up, and power-domain isolation vulnerabilities through Electrical Rule Checking.
• Manage automated dummy metal, poly, and diffusion filling strategies to meet density rules.

What we're looking for

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• 12+ years of relevant experience.
• In-depth knowledge of Foundry rules, DFM, and experience in silicon tape-out and RTO tapeout.
• Experience in running physical verification (LVS, DRC, ERC, PERC) (preferred).
• Experience with EDA tools and flows such as ICV, Calibre, and Pegasus (preferred).
• Rule deck coding experience in ICV, Calibre, or Pegasus EDA tools (preferred).
• Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out (preferred).
• Experience in scripting languages like Python, Tcl, or Perl (preferred).