Senior Verification Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $183k
This role $216k
$125k most similar roles pay here $279k

This role pays more than 82% of similar roles. Most pay $157,038–$208,825 — the shaded band above. At the midpoint, this role pays about $216k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Verification Engineer

The Senior Verification Engineer joins the Display Team to verify GPU and SoC display engines. This role involves defining verification scopes, developing functional and performance testplans, and building scalable UVM-based infrastructure while utilizing agentic AI to automate tasks and accelerate debugging. The engineer will develop UVM testbenches and checkers, work with C/C++ based testbenches, debug HLS designs, and drive coverage closure. Key technical requirements include expertise in SystemVerilog, Verilog, Python, C/C++, and EDA tools like VCS and Verdi. Candidates must possess domain knowledge of display pipelines, including DisplayPort, HDMI, and MIPI DSI/CSI protocols, as well as MMU interactions and low-power features like clock gating. The role focuses on ensuring consistent display IP behavior across diverse tool stacks while solving complex integration issues for products in consumer, professional, automotive, and AI markets.

What you'll do

  • Define verification scope and develop functional and performance testplans for GPU and SoC display engines.
  • Build scalable UVM-based infrastructure and develop UVM testbenches and checkers.
  • Utilize agentic AI to automate repetitive tasks, accelerate debugging, and improve team efficiency.
  • Debug reference models and designs developed in HLS using C/C++ based testbenches.
  • Track metrics and drive coverage closure for high-quality IP products.
  • Partner with architects to reason through architectural solutions and develop silicon-proven designs.
  • Deploy verification flows and debug complex integration issues across diverse tool stacks and organizational boundaries.

What we're looking for

  • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience).
  • 10+ years of relevant experience in verification engineering.
  • Expertise in UVM, SystemVerilog, Verilog, Python, and C/C++.
  • Experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches on shipped silicon.
  • Proficiency with industry EDA tools including VCS, Verdi/Debussy, and GDB.
  • Knowledge of display pipelines, protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction, and system low-power features.
  • Experience with HLS-based designs and pixel processing.
  • Ability to leverage agentic AI to automate tasks and improve team efficiency.

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