Senior Verification Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $216k
$130k $279k
below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $176,043–$217,600 — the blue band above. At the midpoint, this role pays about $216k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Verification Engineer

The Senior Verification Engineer joins the Display Team to verify GPU and SoC display engines. This role involves owning testplan development, verification sign-off, and infrastructure for high-quality IPs across consumer, professional, automotive, and AI markets. Key responsibilities include defining verification scope, developing functional and performance testplans, and building scalable UVM-based infrastructure. The engineer will develop UVM testbenches and checkers, work with C/C++ testbenches, and debug reference models developed in HLS. Required skills include expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, along with proficiency in EDA tools like VCS and Verdi. The role requires deep domain knowledge of display pipelines, including DisplayPort, HDMI, and MIPI DSI/CSI protocols, MMU interaction with ISO clients, and system low-power features like clock gating and power domains.

What you'll do

  • Define verification scope and develop functional and performance testplans for GPU and SoC display engines.
  • Build and maintain scalable UVM-based testbenches, checkers, and infrastructure.
  • Leverage agentic AI to automate repetitive tasks and accelerate the debug process.
  • Develop C/C++ based testbenches and debug reference models and designs developed in HLS.
  • Track verification metrics and drive coverage closure to ensure silicon-proven designs.
  • Partner with architects to reason through architectural solutions and shape micro-architecture decisions.
  • Debug complex integration issues and deploy verification flows across diverse tool stacks and global sites.
  • Verify display protocols including DisplayPort, HDMI, and MIPI DSI/CSI.

What we're looking for

  • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field or equivalent experience.
  • 10+ years of relevant experience.
  • Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++.
  • Experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches.
  • Proficiency with industry EDA tools including VCS, Verdi/Debussy, and GDB.
  • Domain knowledge of display pipelines, protocols (DisplayPort, HDMI, MIPI DSI/CSI), and system low-power features.
  • Prior Display Unit Verification experience with familiarity in pixel processing, ISO performance testing, and HLS-based designs (preferred).
  • Demonstrated experience shaping architectural specifications and micro-architecture decisions (preferred).

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