Mixed-Signal Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$129,300–$225,300 / yr
Posted
4 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k
This role $177k
$116k $255k
below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $177k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Mixed-Signal Verification Engineer

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The Mixed-Signal Verification Engineer joins the wireless silicon development team to support the design of highly energy-efficient wireless SOCs. In this role, you will verify RF and mixed-signal blocks and their interfaces, ensuring silicon-correct functionality and optimal coverage. Daily responsibilities include reviewing specifications, defining verification plans, and developing top and block-level testbenches. You will build and reuse monitors and checkers, debug failures, manage bug tracking, and write scripts for flow automation. Key technical requirements include expertise in SystemVerilog, Verilog, and the UVM framework. You should also possess experience with UPF, Python, Matlab, Virtuoso Composer, ADE, and HED. This position focuses on solving complex verification challenges for wireless systems, utilizing real-numbered analog behavioral models and novel AI-driven methodologies.

Skills

System Verilog UVM Verilog Mixed-Signal Verification RF Python Matlab UPF Virtuoso Composer ADE HED HDL SOC Automation Debugging

What you'll do

  • Review specifications to extract features and execute verification plans.
  • Develop top-level and block-level Mixed Signal and Digital testbenches in a UVM framework.
  • Build and reuse monitors and checkers for RF and Mixed-Signal blocks.
  • Debug failures, manage bug tracking, and analyze coverage to close issues.
  • Write scripts to automate verification flows.
  • Improve Mixed Signal verification methodology using novel ideas and AI.

What we're looking for

  • Minimum requirement of a bachelor's degree.
  • Bachelor degree in technical disciplines with 2+ years of relevant industry experience (preferred).
  • Industry verification experience with RF/Mixed-Signal blocks and SOCs.
  • Expertise building Mixed-Signal testbenches, checkers, and tests using System Verilog.
  • Experience in UVM methodology and HDL (System Verilog, Verilog) for verification.
  • Experience with UPF, Python, or Matlab.
  • Experience with Virtuoso Composer, ADE, and HED.
  • Expertise creating and using real-numbered analog behavioral models in System Verilog (preferred).

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