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ASIC RTL Verilog SystemC VHDL Python Perl Tcl CI/CD Git Linux ARM DDR UCIe AMBA DFT STA CDC Lint Synopsys Cadence Mentor Graphics ModelSim QuestaSIM +19 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

EDA RTL2GDSII ASIC SOC CMOS DFT Scan MBIST LBIST Standard Cells Physical Design Flows +6 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

Verilog SystemVerilog Python Perl Makefile AMBA AXI APB UPF SDC SVA ASIC CAD tools Simulation Synthesis STA LINT LEC CDC RDC Power estimation +14 more Show less

NVIDIA CUDA TensorRT Triton DRIVE Jetson Python C++ Docker Kubernetes AWS Git GitHub CI/CD PostgreSQL Redis Prometheus Grafana Multimodal_foundation_models Vision-Language-Action_(VLA)_models Mixture-of-Experts_(MoE) Transformer Diffusion_model +18 more Show less

Python Perl RTL EDA tools SOC integration Design automation flows Synthesis Padring Physical design +4 more Show less

Verilog Python Perl Unix/Linux Makefiles CI/CD +1 more Show less

SystemVerilog RTL Lint CDC RDC Synthesis STA Memory_subsystems Bus_interfaces CPU_integration DMA_engines Compression Security_IP_design PCIE QSPI UART SPMI Cross_clock_domain_design ASIC_low_power_design Multiple_supply_domains Dynamic_power_scaling Power_analysis DFT Scan_insertion Memory_BIST +20 more Show less

SystemVerilog RTL Lint CDC RDC Synthesis STA MemorySubsystemDesign BusInterfaces CPUIntegration DMAEngines CompressionIP SecurityIP PCIE QSPI UART SPMI CrossClockDomainDesign ASICLowPowerDesign DFT ScanInsertion MemoryBIST +17 more Show less

Verilog CoreSight AXI AHB UPF RTL EDA tools HDL ASIC design flow micro-architecture specifications performance/power correlation debug features test bench development simulation/emulation functional verification +10 more Show less

VLSI RTL Verilog SystemVerilog UVM CoreSight EDA Simulation Emulation Performance Analysis Power Analysis Debugging Techniques ASIC Design Micro-Architecture Test Bench Development CI/CD +11 more Show less

VLSI RTL Verilog SystemVerilog UVM CoreSight EDA Simulation Emulation Performance Analysis Power Analysis CI/CD Git Linux Python Perl Tcl Microprocessor Debug Debug Hub Design Trace Hub Design +15 more Show less

SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC EDA Verilog +7 more Show less

SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC EDA Verilog Python Tcl Makefile Git JIRA Confluence +13 more Show less

SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC SoC HDL Verilog EDA-tools +9 more Show less

Verilog SystemVerilog DFT Spyglass Questa CDC Cadence Conformal VCS TCL Python Perl Perforce IC Manage Git Linux Windows UPF Synopsys Design Compiler Synopsys PrimeTime CI/CD +14 more Show less

Python Tcl Spice Static Timing Analysis CAD Machine Learning Data Science Silicon Verification Power Delivery Analysis Parasitic Extraction Inductance Effects Physical Design Methodology SoC Designs Advanced Technology Nodes Interconnects Performance Analysis +10 more Show less

Python Tcl Spice static timing analysis tools inductance effects parasitic extraction performance analysis power delivery machine learning data science CAD tools Silicon verification methodologies advanced technology nodes SoC design经验 电气工程知识 计算机科学知识 +11 more Show less

Python Tcl Spice static timing analysis tools inductance effects parasitic extraction performance analysis power delivery machine learning data science CAD tools scripting languages Silicon verification advanced technology nodes SoC designs +10 more Show less