Wireless SoC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 67% of similar roles. Most pay $165,150–$209,750 — the shaded band above. At the midpoint, this role pays about $165k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a hardware engineer on a small, high-impact team at Apple, you will play a critical role in designing CPU-based subsystems for advanced wireless SoCs, focusing on achieving optimal power efficiency while meeting stringent performance and area requirements. Your daily tasks will include writing micro-architecture specifications, coding SystemVerilog designs following established guidelines, integrating industry-standard and custom IPs, and collaborating with software, firmware, and platform engineering teams to ensure seamless hardware/software/power partitioning. You will also support verification efforts, use static tools like LINT for design checks, and optimize area, timing, and power metrics. The ideal candidate has a strong background in digital design, SoC architecture, and experience with HDL languages such as Verilog, along with familiarity with low-power design techniques and EDA tools.

Skills

SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC EDA Verilog

What you'll do

Write micro-architecture and design specifications for CPU-based subsystems.
Code designs in SystemVerilog, owning all aspects of RTL development.
Integrate IP blocks and optimize memories/hard macros for the block.
Support verification efforts at multiple levels to ensure quality.
Analyze and optimize area, timing, and power metrics for SoCs.
Collaborate with software teams on hardware/software/power partitioning.

What we're looking for

Extensive experience in CPU-based subsystem design for high-performance, low-power wireless SoCs.
Proficiency in SystemVerilog and other HDL languages for RTL development and IP integration.
Expertise in micro-architecture specification writing and design optimization for area, timing, and power.
Familiarity with industry-standard EDA tools and methodologies for verification and static checks.
Knowledge of low-power design techniques and processor subsystems including AXI/AHB bus fabrics.

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