SoC Physical Design Methodology Engineer

What you'll do

• Create and implement methodologies to improve the power, performance, and area (PPA) of on-chip interconnects.
• Perform electrical analysis to determine how physical effects impact the performance of SoC designs.
• Develop construction methodologies to mitigate PPA degradation identified in silicon.
• Run signoff flows and compare results against measurements from manufactured silicon to ensure accurate modeling.
• Collaborate with standard cell teams to identify new cells that improve yield and engineering productivity.
• Drive updates to production design flows in coordination with CAD and design teams.
• Create strategies to verify theoretical designs through actual silicon testing.
• Apply data science and machine learning techniques to develop and refine physical design methodologies.

What we're looking for

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field.
• At least 3 years of relevant experience.
• Experience with physical design on SoC designs and advanced technology nodes.
• Deep knowledge of interconnects, parasitic extraction, performance analysis, and manufacturing effects.
• Extensive knowledge of power delivery and the impact of power-supply noise on chip performance.
• Proficiency in circuit design, including understanding inductance effects and running/modifying Spice simulations.
• Familiarity with static timing analysis tools and methodologies.
• Proven understanding of scripting languages such as Python and Tcl.