Debug SoC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 72% of similar roles. Most pay $161,350–$216,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Debug SoC Design Engineer

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As a Debug SoC Design Engineer, you will join a dynamic hardware team at the forefront of semiconductor innovation. Your primary responsibility is to own the RTL design for the debug and trace hub, ensuring it meets stringent power, performance, and area goals while collaborating with IP developers and architects. You will develop micro-architectural details in conjunction with silicon and software experts, support verification efforts through test bench development, and assist validation engineers in diagnosing issues using advanced debugging techniques. Familiarity with industry-standard EDA tools and knowledge of debug methodologies like CoreSight are essential, as you work on cutting-edge SoC designs that will impact millions of users globally.

Skills

VLSI RTL Verilog SystemVerilog UVM CoreSight EDA Simulation Emulation Performance Analysis Power Analysis Debugging Techniques ASIC Design Micro-Architecture Test Bench Development CI/CD

What you'll do

Develop RTL for the debug and trace hub to meet power, performance, and area goals.
Define architectural debug features in collaboration with silicon and software experts.
Support verification teams in test bench development and simulation of debug features.
Diagnose suspected bottlenecks or overconsumption by assisting performance/power teams.
Aid validation engineers in using debug features to diagnose SoC-level issues.

What we're looking for

3+ years of experience in RTL development for SoC debug features.
Proven expertise in defining and implementing micro-architectural details for debug systems.
Strong background in functional verification, including test bench development and simulation.
Experience with performance/power analysis to diagnose design bottlenecks.
Knowledge of industry-standard EDA tools and familiarity with CoreSight or similar debug techniques.

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