Wireless SoC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Los Angeles, CA
Salary: $120,300–$210,100 / yr
Posted: 53 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 67% of similar roles. Most pay $165,150–$209,750 — the shaded band above. At the midpoint, this role pays about $165k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a senior hardware engineer on the CPU-based subsystem team, you will play a pivotal role in designing high-performance, low-power wireless SoCs for Apple devices. Your daily responsibilities include writing micro-architecture specifications, coding SystemVerilog designs following established guidelines, and integrating industry-standard IPs into SoCs while optimizing memory and hard macros. You will collaborate closely with software, firmware, and platform engineering teams to ensure hardware/software/power partitioning aligns with project goals. Key skills required are familiarity with the ASIC design flow, digital design, SoC architecture, and proficiency in Verilog or SystemVerilog. Additionally, experience with AXI/AHB bus fabrics, processor subsystems, and low-power design techniques is essential for this highly visible role that demands a deep understanding of industry-standard static tools like LINT, CDC, and RDC.

Skills

SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC SoC HDL Verilog EDA-tools

What you'll do

Write micro-architecture and design specifications for CPU-based subsystems.
Code designs in SystemVerilog, owning all aspects of RTL development.
Integrate IP blocks and optimize memories/hard macros for the block.
Support verification efforts at multiple levels to ensure quality.
Analyze and optimize area, timing, and power metrics for SoCs.
Collaborate with software teams on hardware/software/power partitioning.

What we're looking for

Extensive experience in CPU-based subsystem design for high-performance, low-power wireless SoCs.
Proficiency in SystemVerilog and other HDL languages for RTL development and IP integration.
Expertise in micro-architecture specification writing and conversion to detailed designs.
Knowledge of digital design, SoC architecture, and industry-standard EDA tools like LINT, CDC, RDC.
Experience with AXI/AHB bus fabrics and processor subsystems, including low-power design techniques.
Ability to collaborate effectively across multi-disciplinary teams in the ASIC design process.

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