Wireless SoC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 38 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $183k

This role $165k

$109k most similar roles pay here $230k

This role pays less than 67% of similar roles. Most pay $156,550–$209,750 — the shaded band above. At the midpoint, this role pays about $165k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a Wireless SoC Design Engineer at our cutting-edge wireless SOC organization, you will join a world-class vertically integrated engineering team responsible for developing highly energy-efficient silicon solutions. Your role involves defining microarchitecture in collaboration with architecture, software, and firmware teams to implement RTL that meets performance, power, and area (PPA) targets while adhering to Lint, CDC, and RDC checks. You will work closely with verification, DFT, and physical design teams to optimize IP for SoC integration and support pre-silicon verification and post-silicon validation efforts. This position requires expertise in System Verilog RTL implementation, cross-clock domain design principles, low-power techniques, and ASIC test methodologies, making it ideal for someone skilled in memory subsystems, bus interfaces, and high-speed/low-speed peripherals like PCIe and QSPI.

Skills

SystemVerilog RTL Lint CDC RDC Synthesis STA MemorySubsystemDesign BusInterfaces CPUIntegration DMAEngines CompressionIP SecurityIP PCIE QSPI UART SPMI CrossClockDomainDesign ASICLowPowerDesign DFT ScanInsertion MemoryBIST

What you'll do

Define microarchitecture in collaboration with architecture, software, and firmware teams.
Implement RTL code that meets PPA requirements and passes Lint, CDC, RDC checks.
Optimize IP design for performance, power efficiency, and area during SoC integration.
Support pre-silicon verification and software/firmware development processes.
Assist in post-silicon validation, system integration, and debugging efforts.

What we're looking for

Experience in defining microarchitecture for ASIC design to meet functional requirements.
Proficient in System Verilog RTL implementation adhering to PPA targets.
Skilled in Lint, CDC, RDC checks and synthesis tools.
Expertise in cross-clock domain design principles and low power techniques.
Knowledge of DFT methodologies including scan insertion and memory BIST.
Strong collaboration skills across multiple engineering disciplines.

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