Wireless SoC Design Engineer

Apple Inc

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$126,800–$220,900 / yr
Posted
53 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $174k
$116k most similar roles pay here $232k

This role pays less than 53% of similar roles. Most pay $165,150–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Wireless SoC Design Engineer

As a hardware engineer on a small, high-impact team at Apple, you will play a critical role in designing CPU-based subsystems for advanced wireless SoCs, focusing on achieving optimal power efficiency while meeting stringent performance and area requirements. Your daily tasks will include writing micro-architecture specifications, coding SystemVerilog designs, integrating industry-standard IPs, and collaborating with software and firmware teams to ensure seamless hardware/software co-design. You will also engage in static tool checks like LINT and CDC, optimize design for area, timing, and power, and work closely with multi-disciplinary groups to deliver high-quality ASICs on schedule. This role requires expertise in digital design, SoC architecture, Verilog, and low-power techniques such as UPF, alongside a strong understanding of EDA tools and processor subsystems.

What you'll do

  • Write micro-architecture and design specifications for CPU-based subsystems.
  • Code designs in SystemVerilog, owning all aspects of RTL development.
  • Integrate IP blocks and optimize memories/hard macros for the block.
  • Support verification efforts at multiple levels to ensure quality.
  • Analyze and optimize area, timing, and power metrics for SoCs.

What we're looking for

  • Extensive experience in CPU-based subsystem design for high-performance, low-power wireless SoCs.
  • Proficiency in SystemVerilog and other HDL languages for RTL development and IP integration.
  • Expertise in micro-architecture specification writing and design optimization for area, timing, and power.
  • Familiarity with industry-standard EDA tools and methodologies for verification and static checks.
  • Knowledge of low-power design techniques and processor subsystems including AXI/AHB bus fabrics.

More like this

Similar roles

Wireless SoC Design Engineer

Apple Inc

Los Angeles, CA 53 days ago $120,300$210,100
SystemVerilog RTL SystemC LINT CDC RDC AXI AHB UPF ASIC SoC HDL Verilog EDA-tools

Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 44 days ago $126,800$220,900
SystemVerilog RTL Lint CDC RDC Synthesis STA Memory_subsystems Bus_interfaces CPU_integration DMA_engines Compression Security_IP_design PCIE QSPI UART SPMI Cross_clock_domain_design ASIC_low_power_design Multiple_supply_domains Dynamic_power_scaling Power_analysis DFT Scan_insertion Memory_BIST

Wireless SoC Design Engineer

Apple Inc

San Diego, CA 44 days ago $120,300$210,100
SystemVerilog RTL Lint CDC RDC Synthesis STA MemorySubsystemDesign BusInterfaces CPUIntegration DMAEngines CompressionIP SecurityIP PCIE QSPI UART SPMI CrossClockDomainDesign ASICLowPowerDesign DFT ScanInsertion MemoryBIST

Wireless SOC FW Engineer

Apple Inc

San Francisco, CA 56 days ago $126,800$220,900
C Assembly ARM RTOS Python Perl Tcl Bluetooth WLAN UWB MAC PHY

Wireless SOC FW Engineer

Apple Inc

San Francisco, CA 56 days ago $126,800$220,900
C Assembly ARM RTOS Python Perl Tcl Bluetooth WLAN Zigbee UWB