Senior Manager, ASIC / SoC Design Engineering in San Jose, California | Advanced Micro Devices, Inc

Amd

Hybrid Actively hiring
San Jose, CA Posted 49 days ago $214,400–$214,400 / year
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At a glance

AI generated

TL;DR

AMD is seeking a Silicon Engineering leader to head a team of design engineers responsible for developing next-generation SoC and compute technologies. This role involves driving microarchitecture development, overseeing RTL implementation, and ensuring seamless integration with internal and third-party IP, while also defining and evolving SoC design methodologies. The ideal candidate possesses extensive experience in digital design using Verilog/SystemVerilog, familiarity with SOC tools like Spyglass and Questa CDC, and proficiency in scripting languages such as TCL and Python. Additionally, the role requires strong leadership skills to manage cross-functional teams, hire engineers, and implement AI-driven process improvements, all while delivering complex SoC programs from concept to silicon.

Skills

Verilog SystemVerilog DFT Spyglass Questa CDC Cadence Conformal VCS TCL Python Perl Perforce IC Manage Git Linux Windows UPF Synopsys Design Compiler Synopsys PrimeTime CI/CD

What you'll do

  • Lead microarchitecture development and oversee RTL implementation for SoC technologies.
  • Ensure seamless integration of internal and third-party IP within the SoC design.
  • Define and evolve SoC design methodologies and best practices for future projects.
  • Manage and grow high-performing teams, including hiring and coaching engineers.
  • Drive project execution from planning to tapeout readiness and retrospectives.
  • Improve team processes through AI adoption and traditional automation techniques.

What we're looking for

  • Proven leadership in managing design engineers and cross-functional teams.
  • Extensive experience in digital design with RTL implementation using Verilog/SystemVerilog.
  • Solid understanding of DFT technologies and SOC tools like Spyglass and Questa CDC.
  • Hands-on expertise in specifying timing constraints across multiple clock domains and modes.
  • Background in project planning, execution, and management from microarchitecture to timing closure.
  • Strong communication skills for complex technical information across diverse audiences.
  • Bachelors or Masters degree in computer engineering/Electrical Engineering.

Market check

Salary context

This $214,400–$214,400 range sits above 65% of similar postings on FindRole.

Peer median band

$163,200–$221,700

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$161,720–$223,700

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 80 open roles on FindRole.

Listed pay typically runs $176,400–$176,400 across 80 roles with salary data.

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