ASIC/SoC Design Engineer in San Jose, California | Advanced Micro Devices, Inc

Amd

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $166,400–$166,400 / yr
Posted: 9 days ago
Closes: Jun 2, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k

This role $166k

$152k most similar roles pay here $233k

This role pays less than 73% of similar roles. Most pay $165,450–$222,425 — the shaded band above. At the midpoint, this role pays about $166k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · ASIC/SoC Design Engineer in San Jose, California | Advanced Micro Devices, Inc

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AMD seeks a senior microarchitectural designer to join its Adaptive SoC and FPGA Configuration team. This role involves crafting detailed specifications and implementing RTL for next-generation FPGA configuration controllers, collaborating closely with hardware, firmware, and software teams to ensure seamless integration across all phases of the design cycle. Key responsibilities include driving design from concept through production silicon, integrating complex blocks into full-chip environments, partnering with verification teams for comprehensive coverage, and working with test engineers on DFT features. The ideal candidate has a strong background in ASIC design, proficiency in Verilog, SystemVerilog, and SVA, experience with industry-standard CAD tools, and scripting skills in Perl, Python, and Makefile. Knowledge of AMBA protocols and multi-power domain designs is preferred, making this role crucial for optimizing performance, power, and area metrics in cutting-edge FPGA configurations.

Skills

Verilog SystemVerilog Python Perl Makefile AMBA AXI APB UPF SDC SVA ASIC CAD tools Simulation Synthesis STA LINT LEC CDC RDC Power estimation

What you'll do

Author detailed micro-architecture specification and own RTL implementation of next-gen FPGA Configuration controller.
Drive design from concept through production silicon, including verification and physical design integration.
Integrate complex configuration blocks into full-chip environment to ensure proper connectivity and clock domain crossings.
Partner with verification teams to ensure comprehensive functional coverage for the configuration system.
Work closely with test engineers to implement DFT features and reduce test time.

What we're looking for

Proven experience in ASIC design and microarchitectural specification.
Expertise in Verilog, SystemVerilog, and SystemVerilog Assertions (SVA).
Proficiency with industry-standard CAD tools for simulation and verification.
Strong knowledge of on-chip interconnect protocols like AMBA AXI/AXI-S/APB.
Experience in multi-power domain designs and UPF implementation.
Excellent collaboration skills across hardware and software teams.

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