Wireless SoC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 38 days ago

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k

This role $174k

$116k most similar roles pay here $232k

This role pays less than 55% of similar roles. Most pay $156,550–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Wireless SoC Design Engineer

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As a Wireless SoC Design Engineer at our cutting-edge hardware organization, you will join a world-class vertically integrated team responsible for developing energy-efficient wireless silicon solutions. Your primary responsibilities include defining microarchitecture in collaboration with architecture, software, and firmware teams, implementing RTL code that meets performance, power, and area (PPA) targets, and working closely with verification, DFT, and physical design teams to ensure successful SoC integration from concept through silicon bring-up. You will need expertise in System Verilog, knowledge of Lint, CDC, RDC, Synthesis, and STA, as well as a deep understanding of cross-clock domain design principles and low-power techniques. This role demands strong communication skills and the ability to thrive in a fast-paced environment where you collaborate across multiple functional areas to solve complex engineering challenges.

Skills

SystemVerilog RTL Lint CDC RDC Synthesis STA Memory_subsystems Bus_interfaces CPU_integration DMA_engines Compression Security_IP_design PCIE QSPI UART SPMI Cross_clock_domain_design ASIC_low_power_design Multiple_supply_domains Dynamic_power_scaling Power_analysis DFT Scan_insertion Memory_BIST

What you'll do

Define microarchitecture in collaboration with architecture, software, and firmware teams.
Implement RTL code that meets PPA requirements and passes Lint, CDC, RDC checks.
Optimize IP performance, power consumption, and area by working with physical design teams.
Support pre-silicon verification and software/firmware development processes.
Assist in post-silicon validation and system integration efforts.

What we're looking for

Experience in defining microarchitecture for ASIC design to meet functional requirements.
Proficient in System Verilog RTL implementation adhering to PPA targets.
Knowledge of Lint, CDC, RDC, Synthesis, and STA tools and methodologies.
Expertise in cross-clock domain design principles and low power techniques.
Familiarity with DFT, scan insertion, memory BIST, and other test methodologies.
Strong collaboration skills across multiple engineering disciplines.

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