SoC Physical Design Methodology Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $184,700–$324,800 / yr
Posted: 156 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 92% of similar roles. Most pay $168,425–$227,350 — the shaded band above. At the midpoint, this role pays about $255k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Methodology Engineer

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The SoC Physical Design Methodology Engineer joins a dynamic team focused on creating robust, reliable methodologies to optimize the power, performance, and area of on-chip interconnects. The role involves performing electrical analysis to understand how physical effects impact design performance, developing construction methodologies to mitigate degradation in silicon, and ensuring accurate modeling by running signoff flows compared against actual measurements. You will collaborate with standard cell, CAD, and design teams to update production flows and identify new cells for improved yield and productivity. Key technical requirements include expertise in advanced technology nodes, parasitic extraction, power delivery, and Spice simulations. The position requires proficiency in Python and Tcl scripting languages, as well as knowledge of static timing analysis tools. Additionally, the role may involve applying data science and machine learning to craft these critical design methodologies.

Skills

Physical Design SoC PPA Parasitic Extraction Spice Static Timing Analysis Python Tcl Machine Learning Data Science Circuit Design Signoff Flows Power Delivery Interconnects

What you'll do

Create and implement physical design methodologies to improve the power, performance, and area (PPA) of on-chip interconnects.
Perform electrical analysis to determine how physical effects impact the performance of SoC designs.
Develop construction methodologies to mitigate PPA degradation identified in silicon.
Run signoff flows and compare results against measurements from actual silicon to ensure accurate modeling.
Collaborate with standard cell teams to identify new cells that improve yield and engineering productivity.
Drive updates to production design flows in coordination with CAD and design teams.
Create strategies to verify theoretical designs through silicon testing.
Apply data science and machine learning techniques to develop and refine design methodologies.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Science, or a related field.
10+ years of relevant industry experience.
At least 5 years of physical design experience on SoC designs.
Experience working with advanced technology nodes.
Expertise in interconnects, parasitic extraction, performance analysis, and manufacturing effects.
Knowledge of power delivery and the impact of power-supply noise on chip performance.
Proficiency in circuit design, Spice simulations, and static timing analysis tools.
Proven understanding of scripting languages such as Python and Tcl.

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