Principal Engineer, SOC Design

Samsung Semiconductor

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA · Folsom, CA
Salary: $219,000–$351,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k

This role $285k

$142k most similar roles pay here $373k

This role pays more than 95% of similar roles. Most pay $166,012–$240,800 — the shaded band above. At the midpoint, this role pays about $285k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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View all roles at Samsung Semiconductor

At a glance

TL;DR · Principal Engineer, SOC Design

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As a Principal Engineer in the SOC Design team at Samsung’s DRAM Development Lab, you will play a pivotal role in advancing memory and storage technology for cloud and data center applications. Your responsibilities include defining architectural specifications, overseeing microarchitecture development, and conducting top-level integration of subsystems and chips. You’ll work closely with architects and verification engineers to ensure robust SoC designs while collaborating with physical designers on timing constraints and static timing analysis. Essential skills include hands-on experience in ASIC design flow, ATE vector generation, and commercial IP interfaces such as UCIe, CPU, Ethernet, and DDR controllers. The ideal candidate will have a deep understanding of PPA trade-offs and extensive experience in SoC synthesis, timing analysis, and interfacing with third-party service companies for DFT/PI/PD tasks.

Skills

ASIC RTL Verilog SystemC VHDL Python Perl Tcl CI/CD Git Linux ARM DDR UCIe AMBA DFT STA CDC Lint Synopsys Cadence Mentor Graphics ModelSim QuestaSIM

What you'll do

Define and refine microarchitecture for subsystems or chip-level designs.
Conduct top integration, logic design, RTL implementation, and quality checks.
Review third-party IPs such as ARM cores, DDR controllers, and UCIe PHY.
Integrate third-party IPs and subsystems at the top level of SOC design.
Collaborate with architects and verification engineers to ensure sound SoC design.
Work with physical designers on timing constraints, synthesis, DFT insertion.

What we're looking for

Over 18 years of industry experience in ASIC design and SoC development.
Expertise in ARM cores, DDR interfaces, UCIe, Ethernet, and AMBA bus fabric.
Hands-on knowledge in ATE vector generation, testing, and silicon bring-up.
Proficient in SoC level synthesis, timing analysis, lint check, and CDC checks.
Experience in integrating third-party IPs and subsystems at the top level.

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