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Mechanical Engineering Creo Product Design System Integration Fabrication Design APQP NPI CPI NTI Product Development +5 more Show less

IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan +11 more Show less

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal +10 more Show less

ASIC Package Design Signal Integrity (SI) Power Integrity (PI) High-Speed Routing Power Distribution Networks (PDN) EDA Tools Python Perl TCL Shell Programming Oscilloscopes TDR VNA Silicon Floor Planning Tapeout Hardware Development +11 more Show less

Package Design ASIC SerDes HBM DDR5 Signal Integrity Power Integrity DFx Thermal Modeling Automation Project Management Layout Simulations RF Microwave ADC DAC +12 more Show less

Python C++ VLSI EDA AI ML LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design Package Design HPC +11 more Show less

IC Package Design SI/PI Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux RLGC S-parameters DFM DRC DDR PCIe +14 more Show less

IC Package Design SI/PI Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux RLGC S-parameters DFM DRC DDR PCIe +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux SI/PI RLGC S-parameters DDR PCIe DRC DFM Tape-out +15 more Show less

IC Package Design SI/PI Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux RLGC S-parameters DRC DFM DDR PCIe +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL Calibre CAM350 HFSS PowerSI SI/PI) analysis RLGC S-parameters Unix Linux DFM DRC DDR PCIe +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux SI/PI RLGC S-parameters DDR PCIe DRC DFM Automation +15 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

Semiconductor Package Design 2.5D/3D Packaging Chiplet Architecture EDA Tools Cadence Allegro High-Speed Signaling Thermal Co-design FMEA Physical Failure Analysis Silicon Manufacturing Tapeout BGA +7 more Show less

RF Package Design RF Circuit Design Ansys HFSS ADS Hspice Cadence Allegro Mentor Xpedition MatLab Python C++ Perl Electromagnetics Transmission Line Theory Crosstalk +9 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity Thermal Manufacturability Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout HBM DDR5 RF Microwave ADC DAC +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL Calibre CAM350 HFSS PowerSI SI/PI) analysis RLGC S-parameters DRC DFM Unix Linux DDR PCIe +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL HFSS PowerSI Calibre CAM350 SI/PI) analysis RLGC S-parameter Modeling Unix Linux DFM DRC DDR PCIe +14 more Show less

IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL Calibre CAM350 HFSS PowerSI SI/PI) analysis RLGC S-parameters DDR PCIe Unix Linux DRC DFM Tape-out +15 more Show less

IC Package Design SI/PI Cadence Allegro Mentor Xpedition Calibre CAM350 HFSS PowerSI Python Perl TCL Unix Linux RLGC S-parameters DFM DRC DDR PCIe +14 more Show less