IC Package Design Technical Team Leader

Cisco

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Nov 30, 2026

Market check

Salary context

How this pay compares to similar roles

Similar $204k
$156k $255k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $177,300–$231,300.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · IC Package Design Technical Team Leader

The IC Package Design Technical Team Leader joins the Common Hardware Group to drive complex package design programs for the Silicon One initiative. This role involves leading the San Jose package design team, where you will mentor engineers, manage schedules from concept through tapeout, and oversee the delivery of high-speed, scalable solutions for global networks. You will optimize package pinouts, stack-ups, power distribution, and high-speed routing while collaborating with silicon floor planning, signal integrity, and power integrity teams. Required expertise includes high-speed package design, power distribution networks, and industry-standard EDA tools. Preferred skills include experience with oscilloscopes, TDR/VNA analyzers, and scripting languages like Python, Perl, TCL, or shell programming. You will solve technical challenges related to next-generation ASIC platforms and manufacturing requirements.

What you'll do

  • Lead complex package design programs from initial concept through implementation and tapeout.
  • Optimize package pinouts, stack-ups, power distribution, and high-speed routing for performance and reliability.
  • Coordinate with silicon floor planning, signal integrity, and power integrity teams to ensure system-level alignment.
  • Manage layout editors and implementation teams to deliver high-quality package layouts.
  • Provide technical leadership, direction, and mentorship to the San Jose package design team.
  • Develop team capabilities by mentoring engineers to own increasingly complex package programs.
  • Enhance package design methodologies and partner with vendors to improve product quality and efficiency.
  • Drive innovation in package solutions for next-generation ASIC platforms.

What we're looking for

  • Bachelor’s degree in electrical engineering or related field with 12+ years of experience or Master’s degree with 8+ years of experience.
  • Experience in high-speed package design, including signal integrity considerations and power distribution networks (PDN).
  • Experience with industry-standard EDA tools for package layout and design.
  • Experience with technical leadership in complex hardware or silicon development programs.
  • Extensive experience in ASIC package design, including pinout optimization and high-speed routing (preferred).
  • Knowledge of silicon floor planning and strong collaboration with SI and PI teams (preferred).
  • Experience leading or mentoring engineering teams and developing technical talent (preferred).
  • Experience with testing and measurement equipment, scripting languages like Python, or coordinating cross-functional hardware programs (preferred).

More like this

Similar roles

IC Package Design Engineer

Cisco

San Jose, CA 39 days ago $155,000–$222,600
ASIC Package Design PCB Design SI/PI high‑speed signaling EDA Tools Python Perl TCL Floorplanning stack‑up definition Tapeout multi‑die systems Interposers Power Delivery
5+ yrs exp Hybrid

Senior IC Package Design Engineer

SpaceX

Irvine, CA +1 4 days ago $165,000–$265,000
IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan
5+ yrs exp

System Hardware Board Design Engineering Lead

Cisco

Milpitas, CA 4 days ago $171,600–$245,000
ASIC Hardware Board Design Signal Integrity Power Integrity High-Speed Digital Design Python Cadence Concept Allegro PCIe DDR SerDes Ethernet EMI/EMC Thermal Management Multi-phase Power Conversion Schematic Generation Layout Oscilloscope Logic Analyzer Spectrum Analyzer IEEE Standards 2.5D Fanout Co-packaged Optics Near-packaged Optics
7+ yrs exp

IC Package Design Engineer

Apple Inc

Austin, TX 31 days ago
IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL Calibre CAM350 HFSS PowerSI SI/PI) analysis RLGC S-parameters DDR PCIe Unix Linux DRC DFM Tape-out