IC Package Design Engineer

What you'll do

• Perform physical layout of package substrates for SoC, Memory, RF, and cellular integrated circuits.
• Execute parasitic extraction and S-parameter modeling to validate Signal and Power Integrity performance.
• Own package and SiP physical design from initial concept through tape-out.
• Optimize package structures and configurations to meet system architecture and electrical performance targets.
• Develop automated design and verification flows using Python, Perl, or TCL to improve efficiency.
• Evaluate and integrate new CAD tools and AI technologies to enhance design quality.
• Ensure designs meet design rules (DRC) and design for manufacturability (DFM) standards.

What we're looking for

• BS degree in a relevant field.
• 10+ years of relevant industry experience.
• Proficiency in IC package physical design using Cadence Allegro or Mentor Xpedition platforms (preferred).
• Knowledge of diverse package types such as SiP, PoP, and wirebond, and verification tools like Calibre or CAM350 (preferred).
• Strong understanding of high-speed interface layout constraints (DDR, PCIe) and SI/PI analysis (preferred).
• Experience with simulation tools like HFSS or PowerSI and parasitic extraction (RLGC, S-parameters) (preferred).
• Solid grasp of substrate manufacturing processes, design rules (DRC), and design for manufacturability (DFM) (preferred).
• Proficiency in Python, Perl, or TCL scripting within a Unix/Linux environment (preferred).