IC Package Design Engineer

What you'll do

• Perform physical layout of package substrates for SoC, Memory, RF, and cellular integrated circuits.
• Execute parasitic extraction and S-parameter modeling to validate Signal and Power Integrity performance targets.
• Own the physical design of packages, SiPs, and modules from initial concept through tape-out.
• Optimize package structures and configurations to meet system architecture requirements.
• Develop automated design and verification flows using scripting languages like Python, Perl, or TCL.
• Evaluate new CAD tools and AI technologies to improve design efficiency and quality.
• Ensure designs meet manufacturing constraints including DRC and DFM standards.

What we're looking for

• Bachelor's degree required.
• Experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms (preferred).
• Knowledge of diverse package types such as SiP, PoP, and wirebond (preferred).
• Proficiency with verification tools like Calibre or CAM350 (preferred).
• Expertise in high-speed interface layout constraints for DDR and PCIe (preferred).
• Experience with SI/PI analysis using simulation tools like HFSS or PowerSI (preferred).
• Knowledge of substrate manufacturing processes, DRC, and DFM (preferred).
• Proficiency in Python, Perl, or TCL within a Unix/Linux environment to automate design tasks (preferred).