Senior IC Package Design Engineer

SpaceX

Confirmed live yesterday Trusted

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Work type: On-site
Location: Austin, TXIrvine, CA
Posted: 4 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $209k

$150k $272k

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Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 854 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 591 roles with salary data.

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At a glance

TL;DR · Senior IC Package Design Engineer

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The Sr. IC Package Design Engineer joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. This role involves leading the packaging for custom in-house ASICs and RFICs used in digital beam formers and modems. Key responsibilities include owning package selection, BGA configuration, and package structure, as well as performing layout, optimization, design verification, and tapeout. The engineer must simulate and optimize signal and power integrity and RF performance while coordinating with cross-functional groups on silicon floor plans and pin outs. Required skills include experience with IC package design, substrate design for RF and high-speed die, and tools like Cadence APD+/SIP. Proficiency in SIWave, HFSS, and ADS for EM simulation is also required to solve complex connectivity problems.

Skills

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal

What you'll do

Own and drive advanced package selection, new product BGA configuration, and package structure.
Execute package/SIP layout, optimization, design verification, and tapeout.
Coordinate with cross-functional groups on package selection, feasibility analysis, and design.
Optimize silicon floor plans, bump layouts, and package pin outs based on trade-offs.
Simulate and optimize signal integrity, power integrity, and RF performance of package designs.
Drive methodology, innovations, and productivity improvements in the package design process.

What we're looking for

Bachelor's degree in electrical engineering, computer engineering, or physics.
5+ years of experience with IC package design.
Ability to work extended hours or weekends as needed to meet mission critical deadlines.
Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
Experience with Co-packaged Optics (CPO) (preferred).
Thorough understanding of signal and power integrity fundamentals (preferred).
Substrate design experience for RF, digital, high-speed and mixed signal die (preferred).
Experience with Cadence APD+/SIP or similar design tools (preferred).

IC Package Design Engineer

Apple Inc

San Francisco, CA 30 days ago $129,300–$225,300

IC Package Design Cadence Allegro Mentor Xpedition Python Perl TCL Calibre CAM350 HFSS PowerSI SI/PI) analysis RLGC S-parameters DRC DFM Unix Linux DDR PCIe

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