IC Package Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$184,700–$324,800 / yr
Posted
7 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $255k
$129k $346k
below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $168,500–$227,500 — the blue band above. At the midpoint, this role pays about $255k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · IC Package Design Engineer

The IC Package Design Engineer joins the Packaging team to define, design, and integrate advanced electronic packaging solutions for internal and custom components. This role involves leading package architecture, driving structure and configuration optimization, and owning physical design from concept through tape-out for SoC, memory, RF, and cellular technologies. Key responsibilities include performing physical layout of package substrates, executing parasitic extraction, and conducting S-parameter modeling to meet Signal and Power Integrity targets. The engineer will utilize Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, and PowerSI. Candidates must demonstrate proficiency in substrate manufacturing, design for manufacturability, and high-speed interface layout constraints like DDR and PCIe. Additionally, the role requires using Python, Perl, or TCL scripting within Unix/Linux environments to automate design and verification flows.

What you'll do

  • Perform physical layout of package substrates for SoC, Memory, RF, and cellular integrated circuits.
  • Execute parasitic extraction and S-parameter modeling to validate Signal and Power Integrity performance.
  • Own Package/SiP/module physical design from initial concept through tape-out.
  • Optimize package structure and configuration to meet system co-optimization requirements.
  • Develop automated design and verification flows using Python, Perl, or TCL scripts.
  • Evaluate and integrate new CAD tools and AI tools to enhance design efficiency and quality.
  • Ensure designs meet Design for Manufacturability (DFM) and substrate manufacturing process rules.

What we're looking for

  • BS degree in a relevant field.
  • 10+ years of relevant industry experience.
  • Proficiency in IC package physical design using Cadence Allegro or Mentor Xpedition platforms (preferred).
  • Knowledge of diverse package types such as SiP, PoP, and wirebond, and verification tools like Calibre or CAM350 (preferred).
  • Strong understanding of high-speed interface layout constraints (DDR, PCIe) and SI/PI analysis (preferred).
  • Experience with simulation tools like HFSS or PowerSI and parasitic extraction (preferred).
  • Solid grasp of substrate manufacturing processes, design rules (DRC), and design for manufacturability (DFM) (preferred).
  • Proficiency in scripting languages such as Python, Perl, or TCL in a Unix/Linux environment (preferred).

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