IC Package Design Engineer

What you'll do

• Perform physical layout of package substrates for SoC, Memory, RF, and cellular integrated circuits.
• Execute parasitic extraction and S-parameter modeling to validate Signal and Power Integrity performance.
• Own Package, SiP, and module physical design from initial concept through tape-out.
• Optimize package structure and configuration to meet system co-optimization requirements.
• Develop automated design and verification flows using Python, Perl, or TCL to enhance efficiency.
• Evaluate and integrate new CAD tools and AI technologies to improve design quality.
• Ensure designs meet Design for Manufacturability (DFM) and substrate manufacturing process rules.

What we're looking for

• Bachelor's degree required.
• Experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms (preferred).
• Knowledge of diverse package types such as SiP, PoP, and wirebond (preferred).
• Experience with verification tools like Calibre or CAM350 (preferred).
• Understanding of high-speed interface layout constraints (DDR, PCIe) and SI/PI analysis (preferred).
• Experience with simulation tools like HFSS or PowerSI and parasitic extraction (preferred).
• Knowledge of substrate manufacturing processes, design rules (DRC), and design for manufacturability (DFM) (preferred).
• Proficiency in Python, Perl, or TCL scripting within a Unix/Linux environment (preferred).